Memory Row Refresh Control for Deterministic Row Disturb Mitigation
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Solution Overview
Problem
Existing memory devices face challenges in efficiently identifying and mitigating row disturb effects due to probabilistic row disturb mitigation techniques, which are cumbersome, computationally intensive, and susceptible to attacks, leading to increased power consumption and data degradation.
Innovation Solution
Implementing refresh control circuitry with deterministic row disturb mitigation by tracking a single worst-case count value and address, using counters, a worst-case count register, and comparator circuitry to quickly identify and refresh neighboring memory rows during row disturb events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probabilistic row disturb mitigation techniques are used, then memory devices can handle row disturb effects, but the techniques are computationally intensive and consume excessive power
Solution Approach 1:
The patent segments the row disturb mitigation process by dividing memory rows into groups and using separate counters for each group. This allows the system to track row activations in a structured manner, enabling deterministic identification of worst-case scenarios without requiring computationally intensive probabilistic analysis across all rows simultaneously, thereby reducing power consumption.
Solution Approach 2:
The patent implements preliminary action by pre-configuring worst-case count registers and comparator circuitry before row disturb events occur. The system proactively tracks and identifies potential worst-case scenarios using deterministic counters and comparators, allowing refresh operations to be triggered immediately when thresholds are met, eliminating the need for complex post-event probabilistic analysis and reducing overall computational overhead and power usage.
2Reliability
If probabilistic row disturb mitigation techniques are used, then memory devices can handle row disturb effects, but the techniques are cumbersome and increase computational overhead
Solution Approach 1:
The patent segments the row disturb mitigation process by dividing memory rows into groups and using separate counters for each group. This allows the system to track row activations in a structured manner, enabling deterministic identification of worst-case scenarios without requiring computationally intensive probabilistic analysis across all rows simultaneously, thereby reducing power consumption.
Solution Approach 2:
The patent replaces complex probabilistic computational mechanisms with simpler deterministic hardware mechanisms. Instead of using probabilistic algorithms that require extensive computation, the system employs deterministic counters, worst-case count registers, and comparator circuitry that directly compare counter values against predefined thresholds, significantly reducing computational overhead while maintaining reliability.
3Reliability
If probabilistic row disturb mitigation techniques are used, then memory devices can handle row disturb effects, but they are susceptible to attacks leading to data degradation
Solution Approach 1:
The patent implements preliminary anti-action by proactively identifying and preparing for worst-case row disturb scenarios before attacks can exploit probabilistic vulnerabilities. The deterministic counter and comparator system continuously monitors row activation patterns and triggers refresh operations in advance when predetermined thresholds are reached, preventing data degradation from occurring in the first place rather than reacting to attacks after they manifest.
Solution Approach 2:
The patent enables self-service by allowing the memory system to autonomously monitor its own row activation patterns and automatically trigger refresh operations when deterministic thresholds are exceeded. The worst-case count registers and comparator circuitry provide self-contained protection without requiring external intervention or complex probabilistic decision-making, making the system resistant to attacks that attempt to exploit probabilistic weaknesses.
4Productivity
If deterministic row disturb mitigation is implemented by tracking worst-case count values, then computational overhead is reduced, but additional circuitry components are required
Solution Approach 1:
The patent applies parameter changes by transitioning from probabilistic parameters (randomized refresh intervals, statistical analysis) to deterministic parameters (fixed counters, predefined worst-case thresholds). This parameter transformation enables simpler hardware implementation using standard counter and comparator circuits, improving computational efficiency while the added circuitry represents a straightforward hardware addition rather than complex system architecture.
Data Source
AI summary
Memory with deterministic worst-case row address servicing is disclosed herein. A method of the present technology comprises (1) updating a counter value corresponding to a memory row of a memory device in response to detecting activation of the memory row; (2) comparing the updated counter value to a worst-case count value; and (3) in response to determining that the updated counter value is greater than the worst-case count value, setting the worst-case count value equal to the updated counter value and storing a memory row address of the memory row as a worst-case memory row address. The counter value can be one of a plurality of counter values, each counter value (a) corresponding to a respective memory row and (b) configured to track a number of activations of the respective memory row. The method can further comprise performing a row disturb refresh operation using the worst-case memory row address.