Memory Row Repair via Bit Line Sense Amplifier Data Copying
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory technologies face inefficiencies in yield due to defective memory cells, as treating memories with only a few defective cells as defective products is not economical, and existing post-package repair methods are limited in data transfer efficiency during the repair process.
Innovation Solution
The method involves a memory system with multiple cell arrays, bit line sense amplifier arrays, and dummy bit line sense amplifier arrays, along with bus exchange circuits, to internally copy data from defective rows to redundant rows, enabling efficient data transfer and repair operations without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If redundant memory cells are provided and defect replacement is performed after fabrication, then memory yield is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent pre-allocates redundant row groups and column groups during the memory design stage, preparing replacement resources before defects are detected. This preliminary preparation enables quick defect replacement without adding complex runtime decision-making logic, thus improving yield while controlling complexity.
Solution Approach 2:
The patent copies data from defective memory regions to redundant memory regions using the existing bit line sense amplifier arrays. By reusing existing hardware structures for data copying rather than designing dedicated repair circuits, the patent improves yield while minimizing increases in device complexity.
2Ease of repair
If data copying is performed during post-package repair, then defective cells can be replaced, but data transfer time and repair complexity increase
Solution Approach 1:
The patent designs the bit line sense amplifier arrays to serve dual purposes: normal data read/write operations and data copying for defect replacement. This multi-functionality eliminates the need for separate repair-mode hardware, reducing repair complexity and enabling faster data transfer during post-package repair.
Solution Approach 2:
The patent dynamically configures the bit line sense amplifier arrays to operate in different modes (normal operation mode vs. data copying mode) based on repair needs. This dynamic reconfiguration allows the same hardware to efficiently perform both standard memory operations and defect replacement, reducing both time and complexity overhead.
3Ease of operation
If data is transferred through global input/output lines, then data copying between row groups is enabled, but transfer speed and bandwidth are limited
Solution Approach 1:
The patent segments the data transfer path by introducing local connection pathways between adjacent bit line sense amplifier arrays within the same cell array. This segmentation allows data to be copied locally without traversing the entire global I/O path, significantly improving transfer speed while maintaining the ease of operation for data copying.
Solution Approach 2:
The patent introduces local bit line sense amplifier arrays as intermediary structures that facilitate direct data transfer between row groups within the same cell array. These intermediaries enable faster local data copying compared to using global I/O lines, while still providing a systematic approach to data transfer.
Data Source
AI summary
A method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.