Memory Controller Row Repair With Selective Error-Corrected Copy
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Solution Overview
Problem
Existing memory devices with a few defective memory cells are inefficiently treated as defective products, leading to yield loss, and current post-package repair methods involve data loss and increased power consumption.
Innovation Solution
A memory system with a memory controller that performs a row copy operation after error correction during post-package repair, allowing data to be copied from defective to redundant memory cells without data loss and reducing unnecessary write-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-package repair operation is performed to replace defective memory cells with redundant memory cells, then data integrity is maintained, but power consumption and repair time increase
Solution Approach 1:
The system performs preliminary actions by reading data from the defective row and columns before executing the full row copy operation. The memory controller identifies which columns contain errors and only copies data for those specific columns to the redundant row, rather than copying the entire row. This preliminary identification and selective copying reduces unnecessary write operations and power consumption while maintaining data integrity.
Solution Approach 2:
Instead of performing a complete row copy operation that copies all columns, the system applies partial action by identifying and copying only the columns that contain errors. The memory controller determines the error locations and performs write operations only for those specific columns, thereby reducing power consumption and repair time while still ensuring complete data replacement for the defective cells.
2Reliability
If row copy operation is performed to copy data from defective row to redundant row, then data integrity is ensured, but repair time increases
Solution Approach 1:
The memory controller performs preliminary actions by first reading data from the defective row and identifying error locations before executing the row copy operation. This preliminary data gathering and error identification allows the system to perform targeted copy operations only for columns with errors, significantly reducing the time required compared to copying the entire row.
Solution Approach 2:
The system applies partial action by performing row copy operations only for columns that contain errors rather than copying all columns. The memory controller identifies error locations and performs selective copying, thereby reducing repair time while ensuring data integrity is maintained for all defective cells.
3Reliability
If all memory cells are copied during repair operation, then data integrity is maintained, but unnecessary write operations increase power consumption
Solution Approach 1:
The memory controller performs preliminary actions by reading data from the defective row and identifying which columns contain errors before executing write operations. This preliminary error identification enables the system to perform targeted write operations only for columns with errors, avoiding unnecessary write operations and reducing power consumption while maintaining data integrity.
Solution Approach 2:
The system applies partial action by performing write operations only for columns that contain errors rather than copying all columns. The memory controller determines error locations and performs selective copying, thereby reducing unnecessary write operations and power consumption while ensuring data integrity is maintained for all defective cells.
Data Source
AI summary
An operating method of a memory system includes reading, by a plurality of memory chips, data from a first column of a defective row corresponding to a failure address; generating, by a memory controller, error-corrected data by correcting an error of the read data; and mapping, by a target chip selected from the plurality of memory chips, the failure address to a redundancy address, and writing the error-corrected data to a first column of a redundancy row corresponding to the redundancy address, wherein the reading, the generating, the mapping, and the writing are repeatedly performed on remaining columns of the defective row.