Memory Row Repair Circuitry Using Split Row Slices
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Solution Overview
Problem
Conventional row repair schemes for memory cells are inefficient, often disabling all row repair functionality or applying it to only a portion of memory cells, leading to area and power penalties.
Innovation Solution
A novel row repair scheme that splits memory banks into multiple row slices, allowing separate access and repair of bitcells using distinct row addresses, with dedicated redundancy circuits for each slice, enhancing efficiency and reducing inefficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row repair schemes are applied to all memory cells, then repair coverage is improved, but area and power consumption increase
Solution Approach 1:
The memory bank is divided into multiple row slices, each with its own dedicated redundancy row. This segmentation allows row repair to be applied selectively to specific slices that need it, rather than applying repair mechanisms to the entire memory bank, thus reducing the overall area required for repair functionality while maintaining repair coverage where needed.
Solution Approach 2:
Each row slice is equipped with local redundancy resources and control logic specific to that slice. This local quality approach enables independent repair operations in affected areas without impacting or requiring resources across the entire memory bank, reducing global area and power consumption while maintaining local repair effectiveness.
2Reliability
If conventional row repair schemes are applied to all memory cells, then repair coverage is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory bank into row slices with independent repair control, power consumption is localized to only those slices requiring repair. The control circuitry can activate repair operations selectively in specific slices rather than across the entire memory bank, significantly reducing overall power consumption while maintaining repair coverage for defective regions.
Solution Approach 2:
Each row slice has dedicated but locally-contained repair resources that are activated only when needed in that specific slice. This prevents unnecessary power consumption in slices that do not require repair, while ensuring adequate power resources are available where repair operations are actually performed.
3Area of stationary object
If row repair is disabled or applied to only a portion of memory cells, then area and power penalties are reduced, but repair effectiveness deteriorates
Solution Approach 1:
The memory bank is divided into multiple row slices, each with its own dedicated redundancy row and control logic. This segmentation enables repair to be applied effectively to each slice independently, ensuring that repair resources are concentrated where needed rather than diluted across the entire bank, thus maintaining high repair effectiveness with reduced area overhead.
Solution Approach 2:
The row slice architecture provides universal repair capability across the entire memory bank by tiling multiple identical slice structures. Each slice is self-contained with full repair functionality, allowing any slice to be repaired independently using the same repair mechanisms, thus achieving comprehensive repair effectiveness through modular repetition rather than requiring a single large repair system.
Data Source
AI summary
Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.