Memory Row Selector Using Low-Voltage Transistors for Program Biasing
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Solution Overview
Problem
The use of both low and high voltage transistors in semiconductor memory devices increases manufacturing complexity and chip area due to the need for thicker gate oxide layers in high voltage transistors and additional processing steps for differentiating oxide thickness, which is inefficient and wasteful.
Innovation Solution
A row selector design that uses only low voltage transistors by employing a circuit topology with a number of series-connected transistors equal to the ratio of the voltage difference between programming and inhibit voltages, allowing the transistors to sustain the necessary voltage differences without the need for high voltage components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used to sustain voltage differences higher than supply voltage, then the device can handle high voltage operations, but the chip area increases and manufacturing complexity increases
Solution Approach 1:
The patent divides the high voltage path into multiple segments by connecting several low voltage transistors in series. Each transistor only needs to sustain a fraction of the total voltage difference, specifically the supply voltage or less, which is within their safe operating range. This segmentation allows the circuit to handle high voltage operations without requiring any single transistor to exceed its voltage rating.
Solution Approach 2:
The patent changes the operating parameters of low voltage transistors by configuring them in series arrangements and controlling their gate voltages appropriately. By adjusting the gate control voltages and arranging transistors in specific series configurations, the circuit can sustain high voltage differences across the series combination while each individual transistor operates within its low voltage parameter limits.
2Reliability
If high voltage transistors are used to sustain voltage differences higher than supply voltage, then the device can handle high voltage operations, but the manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The patent uses low voltage transistors for multiple functions: they serve as both the switching elements and the voltage-sustaining elements when connected in series. The same low voltage transistor fabrication process that creates standard logic circuits also creates the series-connected voltage-sustaining structures, eliminating the need for separate high voltage transistor processing steps and masks.
Solution Approach 2:
Instead of the conventional approach of using high voltage transistors to handle high voltage operations, the patent inverts the approach by using multiple low voltage transistors in series. This inversion allows the use of standard low voltage fabrication processes while achieving the same high voltage handling capability, thereby simplifying the manufacturing process.
3Area of stationary object
If low voltage transistors are used with series connection, then the chip area is reduced and manufacturing is simplified, but the circuit topology becomes more complex
Solution Approach 1:
The patent segments the voltage handling function across multiple transistors in series, which reduces the area requirement for each transistor and allows use of smaller low voltage devices. The systematic segmentation pattern (series connections with specific gate control arrangements) provides a regular, repeatable structure that manages the topological complexity through consistency.
Data Source
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Figure 3A
AI summary
A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path (230;215;260) adapted to bias the corresponding word line to a programming voltage when said corresponding word line is selected for selectively performing a program operation on at least one memory cell coupled to the corresponding word line, the first biasing circuit path comprising programming voltage provisioning means (215) adapted to provide the programming voltage; a second biasing circuit path (235) which is adapted to receive, from program-inhibit voltage provisioning means (250) a program inhibit voltage (GND), and to provide to the corresponding word line said program inhibit voltage (GND) when the word line is unselected during the program operation, first biasing means (220,225) for driving the second biasing circuit path in order to control a conduction state thereof; wherein: said first biasing circuit path includes a first transistor (M2) controlled to be electrically conductive when the corresponding word line is selected, and to be electrically non-conductive when the corresponding word line is unselected; said first biasing means controls the second biasing circuit path to be conductive when, during the program operation, the corresponding word line is unselected, said second biasing circuit path includes a plurality of series connected transistors, a number of transistors in said plurality being at least equal to the smallest integer not less than an absolute value of a ratio between a voltage equal to the difference between the programming voltage and the program-inhibit voltage to a predetermined maximum voltage given by the maximum voltage which a transistor of said series-connected transistors can sustain before it breaks down.