Semiconductor Memory Row Activation Stress Compensation
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Solution Overview
Problem
Semiconductor memory devices face data loss issues due to voltage changes caused by frequent activation of specific memory cell rows, which induce stress on adjacent rows, leading to errors in stored data.
Innovation Solution
A method and semiconductor memory device that activate specific memory cell rows and flip data bits in response to concentrated activation, using a control logic system to manage data bit flipping and refresh operations to mitigate stress and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specific memory cell rows are frequently activated, then access speed and productivity are improved, but voltage changes cause stress on adjacent rows leading to data loss
Solution Approach 1:
The patent applies preliminary action by performing a refresh operation on the victim row (adjacent row) before the stress from concentrated activation can cause data loss. The system detects when a specific row is frequently activated and proactively refreshes the adjacent row's data to prevent potential data loss from voltage-induced stress.
2Productivity
If concentrated activation occurs at a specific row, then access efficiency is improved, but stress-induced errors occur in adjacent rows
Solution Approach 1:
The patent converts the harmful effect of concentrated row activation into a beneficial detection opportunity. By monitoring activation patterns, the system identifies when concentrated activation occurs and uses this information to trigger targeted refresh operations on adjacent rows, transforming the potential harm into a proactive protection mechanism.
3Reliability
If refresh operations are performed on adjacent rows, then data integrity is maintained, but additional time and energy are consumed
Solution Approach 1:
The patent applies local quality by performing refresh operations only on specific victim rows adjacent to actively used rows, rather than refreshing the entire memory array. This targeted approach maintains data integrity where needed while minimizing unnecessary refresh operations and their associated time and energy costs.
4Reliability
If data bits are flipped in response to concentrated activation, then stress-induced errors are compensated, but additional control logic complexity is introduced
Solution Approach 1:
The patent implements feedback by monitoring the activation patterns of memory rows and using this information to control refresh operations. The control logic tracks which rows are frequently activated and automatically triggers refresh operations on adjacent rows based on this feedback, creating a closed-loop system that adapts to actual usage patterns.
Data Source
AI summary
Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.