Memory Row Test Pattern Selection for Failure Location Detection
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Solution Overview
Problem
Existing failure analysis methods for memory devices are inefficient due to the inability to effectively detect current abnormalities in circuit blocks that do not receive bias voltage, leading to undetermined states and reduced analysis efficiency.
Innovation Solution
A test device and method utilizing a selection signal generator and test pattern generators to activate specific test operations on memory cell rows based on voltage variations, enabling precise detection of failure locations through indium gallium arsenide microscopy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory device is operated in standby state with limited power supply voltage receiving pad and reference ground voltage receiving pad, then the device complexity is reduced, but the measurement precision of current abnormality detection deteriorates
Solution Approach 1:
The patent segments the power supply configuration by introducing multiple power supply voltage receiving pads (first power supply voltage receiving pad, second power supply voltage receiving pad, etc.) and corresponding power supply circuits (first power supply circuit, second power supply circuit, etc.). This segmentation allows different circuit blocks to receive different bias voltages independently, enabling precise current abnormality detection while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent implements dynamic power supply control where the selection signal generator dynamically selects which power supply circuits to activate based on the test mode selection signal. This dynamic configuration allows the system to adapt the power supply arrangement according to the specific testing requirements, improving measurement precision when needed while maintaining simplicity during normal operation.
2Ease of operation
If the memory device is operated in undetermined state with limited voltage application, then the ease of operation is improved, but the productivity of failure analysis operation deteriorates
Solution Approach 1:
The patent implements preliminary action through the selection signal generator that pre-processes the test signal to generate appropriate test mode selection signals before the actual testing begins. This preliminary signal generation and circuit selection enables the system to quickly identify and activate the correct power supply configurations and test patterns, significantly improving failure analysis productivity while maintaining ease of operation through automated control.
Solution Approach 2:
The patent incorporates feedback mechanisms where the selection signal generator monitors the test signal and generates test mode selection signals based on the detected voltage variations. This feedback loop ensures that the system automatically adjusts the power supply configuration and test patterns to match the actual operating conditions, improving both ease of operation and failure analysis efficiency through adaptive control.
3Device complexity
If only limited power supply voltage receiving pad is used, then the device complexity is reduced, but the reliability of failure analysis deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the power supply function into multiple independent circuits (first power supply circuit, second power supply circuit, etc.), each capable of providing bias voltage to specific circuit blocks. This segmented approach increases reliability of failure analysis by ensuring that all relevant circuit blocks can be independently powered and tested, while maintaining acceptable device complexity through modular design.
Solution Approach 2:
The patent implements multi-functionality through the selection signal generator and test pattern generators that can operate in multiple modes depending on the test signal requirements. The same basic architecture can support different testing scenarios (failure analysis, functionality testing, etc.), improving reliability across different analysis types without proportionally increasing device complexity.
Data Source
AI summary
A test device and a testing method for a memory are provided. The test device includes a selection signal generator and a plurality of test pattern generators. The selection signal generator receives a test signal via a signal input end and detects a voltage variation on the test signal to generate a test mode selection signal. The test pattern generators are coupled between the selection signal generator and a row decoder of the memory device. The test pattern generators receive the test mode selection signal, and one of the test pattern generators is activated according to the test mode selection signal to perform a test operation on at least one of a plurality of memory cell rows in the memory device.