Memory Row Hammer Management Using Count-Based Victim Row Refresh
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Solution Overview
Problem
Existing semiconductor memory devices, particularly DRAMs, face issues with data loss due to leakage currents and the 'row hammer' effect, where frequent access to a word-line leads to charge loss in adjacent cells, necessitating inefficient refresh operations that increase power consumption and overhead.
Innovation Solution
The semiconductor memory device and system manage row hammer by counting access times for each memory cell row, updating count data via time-multiplexed I/O lines, and performing ECC operations on user and count data to reduce overhead, with a row hammer management circuit that determines intensive access and triggers targeted refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data loss from leakage current and row hammer effect, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements a feedback mechanism by counting the number of activations for each word line and using this count information to dynamically determine refresh operations. The counter circuitry monitors access patterns and provides feedback to the refresh control logic, enabling the system to perform refresh operations only when necessary based on actual row hammer susceptibility, rather than using fixed periodic refresh schedules.
Solution Approach 2:
The patent performs preliminary action by proactively counting word line activations and identifying potentially vulnerable rows before data loss occurs. The counter circuitry continuously monitors and accumulates activation counts, allowing the system to detect row hammer patterns early and trigger preventive refresh operations on adjacent memory cells before leakage current causes data corruption.
2Reliability
If comprehensive refresh operations are performed on all memory cell rows, then data reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent applies local quality by targeting refresh operations specifically to memory cell rows that are susceptible to row hammer effects, rather than uniformly refreshing all rows. The system identifies vulnerable adjacent rows based on counter values from intensively accessed word lines and performs localized refresh operations only in those specific regions, leaving other memory areas unaffected.
Solution Approach 2:
The patent segments the memory refresh operation into targeted portions based on row hammer susceptibility. Instead of treating all memory rows uniformly, the system divides refresh operations into segments corresponding to specific adjacent rows that require protection, determined by monitoring activation counts of neighboring word lines.
3Measurement precision
If separate I/O lines and ECC operations are dedicated to count data management, then measurement precision is improved, but device complexity and overhead increase
Solution Approach 1:
The patent merges count data with user data by storing count information in the same memory cell array and using the same I/O lines for both data types. The counter data is integrated into the existing memory structure and communicated through shared global I/O interfaces, eliminating the need for separate dedicated I/O pathways for counting operations.
Solution Approach 2:
The patent implements universality by making the existing I/O lines and ECC engine multi-functional. The same I/O lines that transmit user data are also used to read and write counter data, and the ECC engine performs error correction on both user data and count data, maximizing resource utilization and reducing overall system complexity.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.