Semiconductor Memory Device Sacrificial Patterns
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Solution Overview
Problem
The integration of semiconductor devices is hindered by the difficulty in forming finer patterns due to the need for new and expensive exposure techniques, which limits the high integration of semiconductor devices.
Innovation Solution
A semiconductor memory device design that includes a substrate with a cell array region, interface regions, and sacrificial semiconductor patterns made of polycrystalline silicon, which are strategically placed to enhance device isolation and reduce short-channel effects, allowing for increased integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques are used to form finer patterns, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The device is segmented into distinct regions (cell array region, first interface region, second interface region) with different structural configurations. The first interface region contains sacrificial semiconductor patterns and first recesses, while the second interface region has conventional structures, allowing different regions to be optimized independently for integration and reliability
Solution Approach 2:
Different structural qualities are applied to different regions of the device. The first interface region uses sacrificial semiconductor patterns (polycrystalline silicon) with specific recess configurations to reduce short-channel effects, while other regions use conventional structures, providing locally optimized properties throughout the device
2Productivity
If line widths are reduced for high integration, then productivity is improved, but manufacturing precision deteriorates due to exposure technique limitations
Solution Approach 1:
The solution moves from two-dimensional planar transistors to three-dimensional structures with vertical channels and stacked configurations. The sacrificial semiconductor patterns create defined recesses that enable vertical channel formation, increasing the effective channel area without increasing the planar footprint, thus achieving high integration without requiring finer lateral patterning
3Reliability
If sacrificial semiconductor patterns are added to the first interface region, then reliability is improved, but device complexity increases
Solution Approach 1:
Sacrificial semiconductor patterns (polycrystalline silicon) are introduced in the first interface region and subsequently removed to form first recesses. This extraction process creates the desired structural configuration without permanently adding complex materials, as the sacrificial patterns serve only as temporary structural guides during fabrication
Solution Approach 2:
The sacrificial semiconductor patterns are formed in advance before the final device structure is completed. These patterns pre-define the locations and shapes of the first recesses, allowing subsequent processing steps to proceed with greater precision and reducing the complexity of forming the recesses directly
Data Source
AI summary
A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.