Memory Sampling Clock Phase Adjustment for Data Synchronization
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Solution Overview
Problem
As data transfer rates between host and memory devices increase, the read delay time between the output of the clock signal and the input of data becomes more noticeable, making it difficult for the host device to accurately synchronize with the clock signal, leading to inefficiencies in data transfer.
Innovation Solution
A memory device and host device system that includes a memory controller and a host controller, respectively, to adjust the phase of the sampling clock signal using a tuning pattern signal stored in memory-side and host-side pattern signal storage units, allowing for synchronization of command, data, and status signals, and a sampling clock adjustment unit to fine-tune the sampling clock for accurate data reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data transfer rate is increased, then the productivity is improved, but the synchronization accuracy deteriorates due to increased read delay time
Solution Approach 1:
The patent implements dynamic phase adjustment of the sampling clock based on detected signal characteristics. The host device continuously monitors the relationship between clock signals and data signals, then dynamically adjusts the sampling clock phase to compensate for variable delays, enabling high-speed transfer while maintaining synchronization accuracy
Solution Approach 2:
The system employs feedback mechanisms where the host device detects the actual timing relationship between clock and data signals, then uses this information to adjust the sampling clock phase. This closed-loop control ensures that synchronization accuracy is maintained even as transfer rates increase and delays become more significant
2Speed
If the clock signal frequency is increased, then the data transfer rate is improved, but the read delay time becomes more noticeable, making accurate timing difficult
Solution Approach 1:
The patent changes the phase parameter of the sampling clock dynamically rather than increasing the clock frequency indefinitely. By adjusting the phase offset of the sampling clock based on detected delay characteristics, the system compensates for read delay effects and maintains accurate timing even at high transfer rates
Data Source
AI summary
A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.