Memory Controller Sampling Phase Adjustment for Narrow Data Windows
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Solution Overview
Problem
The shrinking effective sampling window due to increased data rates in memory systems leads to higher sampling error rates and susceptibility to noise interference.
Innovation Solution
A memory controller that dynamically adjusts the sampling phase of the sampling clock signal by generating multiple delayed versions of the data strobe signal and comparing these to select the optimal data signal, thereby expanding the effective sampling window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data rate is increased, then the productivity of memory data transfer is improved, but the effective sampling window shrinks leading to higher sampling errors
Solution Approach 1:
The patent implements dynamic adjustment of the sampling clock phase based on detected data patterns. The sampling circuit dynamically selects between different sampling clock phases (first phase for rising edge, second phase for falling edge) depending on the transition state of the data signal, thereby adapting the sampling window to maintain optimal sampling accuracy across varying data rates
Solution Approach 2:
The patent changes the timing parameter of the sampling clock signal by introducing phase adjustment mechanisms. The sampling clock is dynamically phased to align with data signal transitions, effectively expanding the sampling window duration without increasing the fundamental clock frequency, thus maintaining sampling accuracy at higher data rates
2Device complexity
If the sampling clock phase is not well selected, then the device complexity is reduced, but sampling errors increase leading to data integrity issues
Solution Approach 1:
The sampling circuit automatically detects the transition state of the data signal and self-adjusts the sampling clock phase accordingly. The circuit monitors whether the data signal transitions from low to high or high to low, and autonomously selects the appropriate sampling phase without requiring external intervention or complex control logic
Solution Approach 2:
The patent implements a feedback mechanism where the sampling circuit monitors the data signal transitions and adjusts the sampling clock phase based on detected patterns. The system continuously observes data transitions and dynamically phases the sampling clock to match the actual signal behavior, ensuring optimal sampling timing adapt
3Measurement precision
If the effective sampling window is expanded by delaying data signal, then the sampling accuracy is improved, but the device complexity increases due to additional delay circuits
Solution Approach 1:
The sampling circuit is designed to handle multiple sampling scenarios using a unified architecture. The same sampling circuit can operate with different sampling clock phases depending on the data transition state, eliminating the need for separate sampling paths for rising and falling edges. The delay circuits are integrated into the existing sampling architecture rather than being added as separate components
Solution Approach 2:
The patent merges the delay functionality into the existing sampling clock generation circuitry. Instead of adding separate delay circuits for each sampling path, the solution combines phase adjustment capabilities within the central sampling clock generator, allowing a single circuit to serve multiple sampling phase requirements
Data Source
AI summary
A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.