Memory Block Scan Cadence for Charge Loss Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices experience varying and non-uniform threshold voltage distribution shifts due to slow charge loss over time, making it difficult to predict an optimal threshold voltage offset for error correction without compromising performance.
Innovation Solution
Implementing adaptable charge loss scanning cadence by grouping blocks into block families based on similar programming time and temperature, and periodically scanning these families to reassess and adjust threshold voltage offsets, while limiting the number of simultaneous scanning operations to maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge loss scanning is performed frequently to track threshold voltage shifts, then reliability is improved, but productivity deteriorates due to increased scanning operations
Solution Approach 1:
The patent implements dynamic scanning cadence adjustment where the scanning frequency is not fixed but adapts based on charge loss characteristics. Different block families are scanned at different intervals depending on their programming time and temperature history, allowing the system to maintain reliability while optimizing productivity through selective scanning.
Solution Approach 2:
The patent applies different scanning strategies to different block families based on their specific characteristics. Blocks programmed at different times and under different temperature conditions are grouped into families and scanned according to their individual charge loss profiles, rather than applying a uniform scanning frequency to all blocks.
2Device complexity
If uniform scanning cadence is applied to all blocks, then device complexity is reduced, but reliability deteriorates due to non-uniform charge loss characteristics
Solution Approach 1:
The patent segments blocks into different families based on programming time and temperature characteristics. This segmentation allows each family to be managed with appropriate scanning cadence tailored to its charge loss behavior, improving reliability while maintaining manageable complexity through systematic classification.
Solution Approach 2:
The patent changes the scanning parameter (cadence) based on block family characteristics. By adjusting the scanning interval according to programming time and temperature history, the system optimizes both reliability and complexity, avoiding the need for overly complex control mechanisms while achieving family-specific optimization.
3Productivity
If multiple scan operations are performed simultaneously, then productivity is improved through parallel processing, but reliability deteriorates due to activity spikes
Solution Approach 1:
The patent implements periodic scanning where scan operations are distributed over time rather than executed simultaneously. By scheduling scans at different intervals for different block families, the system achieves parallel processing progress while preventing activity spikes that would compromise reliability and performance consistency.
Data Source
AI summary
A system includes a memory device and a processing device operatively coupled with the memory device to perform operations including determining to perform a first scan operation on a first block of a plurality of blocks of the memory device; responsive to determining to perform the first scan operation, adding an indication of the first scan operation to a queue of pending scan operations corresponding to scanning the plurality of blocks; determining whether a number of pending scan operations of the queue of pending scan operations satisfies a threshold condition; and responsive to determining that the number of pending scan operations does not satisfy the threshold condition, causing a first subset of scan operations of the queue of pending scan operations to be performed on respective blocks of the plurality of blocks.