Memory Scan Chain Debugging with Replaced Data Injection

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Solution Overview

Problem

Conventional memory system debugging methods are time-consuming and inefficient, particularly when multiple flip-flops need to be reconstructed for error detection, as they often rely on repetitive sequences and external data extraction.

Innovation Solution

A method and system that replaces data values in a memory device based on detected errors, allowing for efficient error detection by generating replacement commands to invert data values and scan out data for analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the conventional scan-dump method is used to debug memory systems, then errors can be detected by extracting data items from the scan chain, but the debugging process takes a lot of time and cannot reconstruct multiple flip-flops at once

Engineering Contradiction:
Improveerror detection capabilityVSAvoiddebugging time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-loading test patterns into the scan chain before the actual debugging operation. The scan chain is pre-configured with test data that will be used to detect errors in multiple flip-flops simultaneously, eliminating the need for repeated sequential testing and reducing overall debugging time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple error detection operations into a single scanning process. By combining the test pattern loading, scanning, and error detection into one integrated operation, the system can detect errors in multiple flip-flops at once rather than testing each flip-flop separately, thereby significantly reducing debugging time while maintaining error detection precision.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If the conventional debugging method extracts all data items from the scan chain to detect errors, then comprehensive error detection is achieved, but the process is time-consuming and inefficient

Engineering Contradiction:
Improveerror detection accuracyVSAvoiddebugging efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the essential test patterns needed for error detection from the complete data set, rather than processing all data items. By taking out and using only the necessary test patterns, the system achieves comprehensive error detection while reducing the time and computational resources required for debugging.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by using a subset of test patterns that are sufficient for detecting errors in the scan chain, rather than exhaustively testing every possible data combination. This partial testing approach maintains error detection reliability while significantly improving debugging efficiency by avoiding unnecessary testing operations.

Inventive Principle:
Principle #16Partial or excessive action

3Stability of the object's composition

If the same sequence is repeatedly used for debugging in the scan-dump method, then consistent testing of the same scenario is achieved, but the method cannot detect errors efficiently across different data items

Engineering Contradiction:
Improvetest sequence consistencyVSAvoiderror detection coverage
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamics by making the test sequence adaptive rather than static. The scanning operation can dynamically adjust which data items are tested based on the specific debugging needs and error patterns being investigated, allowing the same debugging infrastructure to handle both repeated consistent testing and varied error detection scenarios efficiently.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12620451B2Memory system, debugging device, debugging method of memory system, and method of operating memory system
Publication Date: 2026.05.05 SAMSUNG ELECTRONICS CO LTD
  • US12620451B2 patent drawing
  • US12620451B2 patent drawing
  • US12620451B2 patent drawing

AI summary

A memory system includes: a memory device configured to store a plurality of data items; a scan chain configured to receive the plurality of data items and to generate scan-out data for the plurality of data items; and a controller configured to replace the scan-out data with replaced data. The scan chain is further configured to receive the replaced data from the controller.