Memory Scan Chain Testing Column Redundancy Logic Multiplexers
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Solution Overview
Problem
Existing memory designs with column redundancy lack effective testing mechanisms for errors in redundancy logic and multiplexers, leading to potential read or write errors due to undetected defects.
Innovation Solution
The memory design incorporates a DFT scan chain that tests column redundancy logic and multiplexers by routing shift-in signals through write and read column redundancy multiplexers, processing them through write drivers and sense amplifiers, and latching the results in data output latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DFT scan chains are used, then the memory can be manufactured and operated, but errors in redundancy logic or redundancy multiplexers cannot be detected
Solution Approach 1:
The scan chain is configured to serve multiple functions: it can test normal data paths and simultaneously test redundancy logic and multiplexers by selectively enabling different signal routing modes. The same scan chain infrastructure is used for both operational testing and redundancy path testing, eliminating the need for separate dedicated test paths.
Solution Approach 2:
The scan chain configuration is made dynamic through control signals that can switch between different operational modes. The redundancy multiplexers are controlled to route signals either through normal operational paths or through test paths that expose redundancy logic, allowing the system to adapt its testing capability based on the test phase without permanent structural changes.
2Reliability
If column redundancy logic and multiplexers are tested, then reliability is improved, but additional testing circuitry and complexity are required
Solution Approach 1:
The redundancy multiplexers and logic circuits are designed to be self-testing through the scan chain mechanism. By routing scan signals through the redundancy paths and observing the outputs, the system automatically tests its own redundancy components without requiring external test equipment or additional dedicated test circuits, thus achieving reliability improvement with minimal added complexity.
3Reliability
If scan chain routes through write driver and sense amplifier, then comprehensive testing is achieved, but signal processing time increases
Solution Approach 1:
The scan chain operates in periodic cycles where test signals are applied in discrete time steps synchronized with clock edges. This allows the signal to propagate through the write driver and sense amplifier in controlled intervals, enabling comprehensive testing while maintaining predictable timing and avoiding continuous signal processing delays that would occur with asynchronous testing approaches.
Data Source
AI summary
A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.