Memory Scan Layout for Stuck-At Fault Detection With Less Area
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Solution Overview
Problem
Conventional DFT techniques for integrated circuits (ICs) result in significant area and height increases in the control section of system-on-chip (SOC) designs due to the use of flip flops for scan testing, leading to design and manufacturing challenges such as increased size, routing issues, power distribution problems, and higher production costs.
Innovation Solution
A fault detection logic is implemented in the control section of the memory system to detect and pinpoint stuck-at faults without the need for separate flip flops for each input, using logic circuits that output specific values based on input equality, allowing for efficient stuck-at-0 and stuck-at-1 testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DFT techniques using separate flip flops for each input are used in the control section, then stuck-at fault detection capability is improved, but area overhead and control section height increase significantly
Solution Approach 1:
Multiple scan chain inputs are merged into a single shared scan chain. Instead of having separate flip flops for each input signal (address, control, debug), the patent combines these inputs into one scan chain that sequentially receives test data for all inputs, thereby reducing the total number of flip flops and control section area while maintaining complete stuck-at fault detection capability
Solution Approach 2:
The single scan chain is designed to serve multiple functions by sequentially testing different input types (address inputs, control inputs, debug inputs). The scan chain can be configured to receive test patterns for any input group, making it a universal testing mechanism that replaces multiple dedicated scan chains
2Reliability
If the control section height is increased to accommodate more flip flops, then comprehensive fault coverage is improved, but signal routing complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple input test paths into a single scan chain pathway, simplifying the signal routing architecture. Instead of routing separate test signals to multiple flip flops distributed throughout the control section, all test signals are routed through one centralized scan chain, reducing routing complexity and manufacturing difficulty
3Adaptability or versatility
If separate flip flops are used for each input in the control section, then individual input testing capability is improved, but area overhead increases
Solution Approach 1:
The scan chain is designed to be dynamically reconfigurable, allowing it to sequentially test different input types (address, control, debug inputs) at different time periods. This dynamic time-multiplexing approach maintains the ability to individually test each input while using a single shared scan chain resource instead of dedicated flip flops for each input
Solution Approach 2:
The patent transitions from a spatial arrangement (multiple parallel flip flops for different inputs) to a temporal arrangement (single scan chain testing inputs sequentially over time). By moving the testing capability to the time dimension, the patent maintains comprehensive individual input testing capability while dramatically reducing the spatial area required in the control section
Data Source
AI summary
A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.