Mixed-Signal Memory Scan Testing Bypass
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Solution Overview
Problem
Current methods for testing semiconductor devices with memory cells, such as EEPROM, are inefficient due to the time-consuming write and read processes, which multiply the testing time across millions of devices, making them costly and inefficient.
Innovation Solution
Implementing a mixed signal device with both digital and analog portions, where the analog portion includes memory cells and selector devices accessible via the digital portion, allowing for pattern loading and unloading using a load clock and system clock, respectively, enabling bypassing of memory cells during testing to reduce testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional EEPROM write and read methods are used for testing, then memory cell functionality can be verified, but testing time becomes excessively long
Solution Approach 1:
The patent divides the testing process into two distinct modes: memory scan mode for fast pattern transfer and logic scan mode for traditional functional testing. By segmenting the test methodology, the patent enables selective use of fast transfer paths for pattern loading while reserving traditional methods for actual functional verification, thereby reducing overall testing time without compromising reliability
Solution Approach 2:
The patent introduces a bypass multiplexer as an intermediary component that can route test patterns directly from the input data buffer to the output data buffer, circumventing the slow EEPROM write and read process. This intermediary provides a fast transfer path that maintains test validity while eliminating the time penalty of traditional memory access
2Reliability
If full EEPROM test procedures are performed on all devices, then comprehensive functionality is ensured, but testing cost and time multiply across millions of devices
Solution Approach 1:
The patent implements dynamic testing where the test methodology adapts based on device characteristics. Devices with passing memory scan tests can proceed to logic scan testing without repeating full EEPROM procedures, while only failing devices undergo comprehensive memory re-testing. This dynamic approach maintains high reliability while dramatically improving productivity for the majority of functional devices
3Reliability
If memory cells are included in the test path, then memory functionality is tested, but testing speed decreases due to write and read time requirements
Solution Approach 1:
The bypass multiplexer serves as a mediator that can switch between two paths: the traditional path through memory cells for functional verification, and a fast path that bypasses memory cells for pattern transfer. This intermediary enables the system to achieve high speeds during pattern loading while maintaining the ability to test memory functionality when needed
Data Source
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AI summary
A method is provided for testing a semiconductor device that includes both a digital (310) and analog (320) portion. The digital portion may include a plurality of latch devices (361-364), and the analog portion may include a plurality of memory cells (321) and a plurality of selector devices (325). Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch devices, and is controlled by a selector input (215). A load clock (372) is applied to load a pattern into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.