Memory Scan Write-Through Testing for Manufacturing Fault Detection
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Solution Overview
Problem
Existing memory devices face challenges in efficiently identifying and addressing manufacturing faults during testing, particularly in the presence of various fault types such as assertion, behavioral, bridging, delay, and gate-delay faults, which can affect the reliability and performance of the devices.
Innovation Solution
A testing environment and methodology that includes shift, capture, and scan modes of operation, utilizing serial and parallel data sequences to test memory devices and other electronic components for manufacturing faults, enabling scan synchronous-write-through (SWT) testing to identify and stress potential faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used to test memory devices, then the testing process is simpler, but the ability to detect manufacturing faults (assertion, behavioral, bridging, delay, and gate-delay faults) is insufficient
Solution Approach 1:
The testing architecture is segmented into multiple specialized components: scan chain for sequential fault detection, pattern generator for creating test vectors, response analyzer for evaluating results, and multiple test modes (scan, functional, boundary scan). This segmentation allows each component to specialize in specific fault detection tasks, improving overall detection precision without overwhelming complexity
Solution Approach 2:
Boundary scan cells are introduced as intermediary elements between memory cells and external pins. These boundary scan cells act as mediators that capture and transfer test data through the memory device, enabling detection of faults that would otherwise be inaccessible to conventional testing methods while maintaining a manageable testing architecture
2Measurement precision
If comprehensive fault detection is implemented, then manufacturing fault detection accuracy improves, but power consumption during testing increases
Solution Approach 1:
The testing architecture implements periodic action through clocked scan chains and sequential test cycles. Test data is shifted through the scan chain in periodic clock cycles, and multiple test patterns are applied sequentially. This periodic operation allows comprehensive fault detection to be distributed over time, reducing peak power consumption compared to simultaneous activation of all test components
Solution Approach 2:
The boundary scan functionality is extracted as a separate, optional testing mode that can be activated only when needed for specific fault types. During normal operation or less demanding tests, the boundary scan cells remain inactive, extracting their power consumption from the continuous operation and allowing comprehensive fault detection to be performed selectively, thus managing overall power consumption during testing
Data Source
AI summary
An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.