Memory Scheduler Frequency Mismatch Bubbles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems with frequency mismatch bubbles, existing technologies face inefficiencies in delivering commands due to frequency differences between memory controller and DRAM chips, leading to delayed signal delivery and reduced command throughput.
Innovation Solution
The solution involves scheduling commands to be delivered during frequency mismatch bubbles by placing them in the B slot before the bubble occurs, allowing for increased efficiency in providing commands from the memory controller to DRAM chips, and utilizing a buffer that can handle multiple commands concurrently or in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are scheduled during frequency mismatch bubbles, then command delivery efficiency is improved, but signal timing synchronization becomes more complex
Solution Approach 1:
The scheduler proactively identifies frequency mismatch bubbles in advance and pre-schedules commands to be delivered during these bubbles. By performing the scheduling action beforehand rather than reactively, the system can utilize the idle conductor periods efficiently while maintaining proper synchronization through advance planning.
Solution Approach 2:
The scheduler acts as an intermediary between the memory controller and DRAM chips, intelligently routing commands during frequency mismatch bubbles when conductors are idle. This intermediary function allows the system to absorb the timing complexity within the scheduler rather than propagating it throughout the entire memory system.
2Productivity
If multiple commands are delivered concurrently using buffer, then command throughput is improved, but buffer resource requirements increase
Solution Approach 1:
The buffer enables continuous command delivery by decoupling the memory controller's command generation from the DRAM chips' command processing. Commands are loaded into the buffer during frequency mismatch bubbles when conductors are idle, ensuring that the buffer is continuously replenished without requiring additional high-speed conductors, thus maintaining useful action continuity with existing resources.
3Productivity
If frequency mismatch bubbles are utilized for command delivery, then conductor utilization is improved, but timing precision requirements increase
Solution Approach 1:
The system employs feedback mechanisms where the scheduler monitors the frequency relationship between the memory controller and DRAM chips, identifies when bubbles occur, and adjusts command scheduling accordingly. This closed-loop feedback allows the system to adapt to timing variations and maintain precise delivery during bubbles without requiring excessive margin in the timing specifications.
Data Source
AI summary
In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described.