Memory Scheduler Power Management for Phase Change Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase change memory (PCM) devices face high power consumption during write operations due to the need for large currents over short periods, which can exceed allowable power limits, necessitating efficient scheduling to manage energy usage.
Innovation Solution
A scheduler for memory systems that includes a pattern storage part with multiple storage patterns for process sequences and a pattern selector to generate schedules that execute external instructions within these patterns, optimizing power consumption by sequencing read and write operations to stay within allowable power ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write operations are performed in PCM devices using large currents over short periods, then write speed is improved, but power consumption exceeds allowable limits
Solution Approach 1:
The scheduler dynamically adjusts the timing and sequencing of write operations based on real-time power consumption levels. By making the scheduling adaptive rather than fixed, the system can accelerate writes when power is available and slow down or pause when power limits are approached, resolving the contradiction between write speed and power consumption constraints
Solution Approach 2:
The system employs periodic scheduling of write operations with variable intervals. Instead of continuous high-current writes, the scheduler introduces periodic gaps between write operations to allow power consumption to return to acceptable levels, enabling sustained high-speed operation within power limits through rhythmic operation patterns
2Productivity
If multiple operations are executed independently with queues and pipelines, then productivity is improved, but power consumption management becomes complex
Solution Approach 1:
The scheduler segments the instruction queue into multiple operation types (read operations, write operations, and idle operations) and processes them through separate handling logic. This segmentation allows independent optimization of each operation type while maintaining overall productivity, reducing the complexity of managing mixed operation streams
Solution Approach 2:
The scheduler is designed as a universal control unit that can handle multiple operation types (reads, writes, and idle operations) through a unified scheduling framework. This multi-functional approach consolidates what would otherwise require separate scheduling mechanisms, reducing overall system complexity while maintaining high productivity through parallel operation management
Data Source
AI summary
A scheduler of a memory system is provided. The scheduler may include a pattern storage part and a pattern selector. The pattern storage part may have a plurality of storage patterns, each of the storage patterns provide for a process sequence for a plurality of instructions. The pattern selector may be configured to select one of the plurality of storage patterns in the pattern storage part and generate a schedule such that external instructions are executed in the process sequence set by the selected storage pattern.