Memory Controller Scheduler Adjusting Write Command Period
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Solution Overview
Problem
Next-generation memory devices require high capacity, non-volatile, low power consumption, and fast operation, which existing semiconductor memory systems struggle to achieve efficiently, particularly in managing write operations and reducing operating time.
Innovation Solution
A semiconductor memory system with a data determination circuit and scheduler that adjusts the generation period of write commands based on input data logic levels, utilizing phase-change resistive layers to optimize write operations by changing the crystallization time, thereby reducing write operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the write command generation period is fixed, then the memory system operates with simple control logic, but the write operation time cannot be optimized for different data patterns
Solution Approach 1:
The patent implements a dynamic write command generation period that adapts based on the data pattern being written. The control logic analyzes whether consecutive data values are identical or different, and automatically adjusts the write command generation timing accordingly. This dynamic adjustment optimizes write speed for different data patterns without requiring complex manual configuration.
Solution Approach 2:
The patent changes the temporal parameter (write command generation period) based on the characteristics of the input data. When data values are identical, a longer generation period is used; when data values differ, a shorter generation period is applied. This parameter adaptation allows the system to optimize write operations for different scenarios while maintaining manageable control logic.
2Productivity
If the write command generation period is shortened to increase speed, then productivity improves, but the reliability of phase-change memory operations may deteriorate
Solution Approach 1:
The patent dynamically adjusts the write command generation period based on the actual data pattern being written. By analyzing whether consecutive data values are identical or different, the system selects an appropriate generation period that ensures reliable phase-change operations while maximizing speed. This dynamic adaptation prevents unreliable operations by not uniformly shortening the period.
Solution Approach 2:
The patent changes the write command generation period parameter according to data characteristics. When data values are identical (requiring longer crystallization time), a longer generation period is maintained for reliability. When data values differ, a shorter generation period is applied to increase speed. This conditional parameter adjustment balances reliability and productivity.
3Loss of time
If the memory system uses fixed timing for write operations, then the control logic remains simple, but the operating time cannot be reduced for identical data patterns
Solution Approach 1:
The patent performs preliminary analysis of the input data pattern before generating write commands. The control logic detects whether consecutive data values are identical or different in advance, and pre-determines the appropriate write command generation period. This preliminary action allows the system to optimize timing without adding complex real-time adjustment mechanisms.
Solution Approach 2:
The patent changes the write command generation period parameter based on detected data patterns. When identical data patterns are detected, the system extends the generation period to reduce unnecessary operations and save time. When different data patterns are detected, the system uses a shorter period. This parameter adaptation reduces operating time while keeping detection logic manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces write operation time by adjusting the write command generation period, enhancing the efficiency and speed of memory operations while maintaining non-volatile characteristics.
Implementation Method 1
each of phase-change material layers in the plurality of memory cells being in any of a set resistance state and a reset resistance state
Implementation Method 2
setting a generation period of a write command based on a crystallization time when all logic levels of the input data are equal to each other, the crystallization time being a time the phase-change material layer takes to be in the reset resistance state
Data Source
AI summary
A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.