Memory Subsystem Command Scheduling for Read Write Latency

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Solution Overview

Problem

Existing memory sub-systems do not effectively consider the time difference between executing commands based on the type and location of memory access, leading to inefficiencies in scheduling commands, particularly between read and write operations across different memory dies.

Innovation Solution

The memory sub-system schedules command execution by differentiating between read and write operations, prioritizing sequential access on the same memory die for read commands and different memory dies for write commands to minimize latency and maximize throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If commands are scheduled without considering memory die location and command type, then scheduling is simple, but latency increases and throughput decreases

Engineering Contradiction:
Improvecommand throughputVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the command scheduling process into distinct handling paths for read commands and write commands. Read commands are scheduled to access the same memory die sequentially, while write commands are scheduled to access different memory dies. This segmentation resolves the contradiction by creating specialized scheduling logic for each command type, improving throughput without requiring a completely complex unified scheduling system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating read commands and write commands differently based on their specific characteristics. Read commands receive scheduling optimized for same-die sequential access, while write commands receive scheduling optimized for cross-die access. This differentiated approach improves overall productivity by matching the scheduling strategy to the local requirements of each command type.

Inventive Principle:
Principle #3Local quality

2Speed

If read commands are executed on different memory dies, then parallelism increases, but access time increases due to location differences

Engineering Contradiction:
Improvecommand execution speedVSAvoidcommand execution latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-scheduling read commands to target the same memory die before execution begins. The memory sub-system controller analyzes incoming read commands and groups them by destination memory die, ensuring that sequential read commands are directed to the same die in advance. This preliminary organization minimizes access time by avoiding unnecessary die switches during command execution.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If write commands are executed on the same memory die, then scheduling is simpler, but throughput decreases due to sequential access requirements

Engineering Contradiction:
Improvewrite command throughputVSAvoidwrite scheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments write command scheduling to distribute write operations across different memory dies. By analyzing the destination addresses of write commands and routing them to different dies when possible, the system achieves parallel write execution. This segmentation increases throughput without requiring complex inter-die coordination, as each die independently handles its assigned write commands.

Inventive Principle:
Principle #1Segmentation

4Ease of operation

If command scheduling ignores memory die location, then scheduling logic is simpler, but latency increases due to unnecessary die switches

Engineering Contradiction:
Improvescheduling logic simplicityVSAvoidcommand execution latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies local quality by implementing location-aware scheduling specifically for read commands. The controller examines the memory die location information in read command addresses and uses this local information to optimize scheduling decisions. This approach maintains relative simplicity in the overall scheduling logic while reducing latency through location-conscious command grouping and execution.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11726815B2Scheduling command execution
Publication Date: 2023.08.15 MICRON TECHNOLOGY INC
  • US11726815B2 patent drawing
  • US11726815B2 patent drawing
  • US11726815B2 patent drawing

AI summary

Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.