Memory Data Scrambling With ECC for NAND Write Error Reduction
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Solution Overview
Problem
Nonvolatile memory devices, such as NAND-type flash memory, PCRAM, MRAM, NFGM, RRAM, and polymer RAM, face reliability issues due to cell-to-cell interference and narrow read margins, leading to high error rates, which necessitate the use of error correction codes to guarantee data integrity.
Innovation Solution
A memory system comprising a memory controller with a scrambler, ECC encoder, ECC decoder, and descrambler to randomize and encode data, correct errors, and restore the original bit sequence, thereby reducing write errors and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced process techniques and MLC techniques are used to increase integration density, then the number of bits stored per cell increases, but cell-to-cell interference occurs and data errors increase
Solution Approach 1:
The patent applies preliminary action by performing scrambling operations on data before it is written to the memory device. The scrambler randomizes the bit patterns in advance to prevent harmful patterns that could cause cell-to-cell interference or read disturbances, thereby proactively addressing reliability issues before they occur during storage or retrieval operations
Solution Approach 2:
The patent introduces an intermediary mechanism through the use of ECC (Error Correction Code) encoding and decoding circuits. The ECC encoder adds redundant check bits to the data before storage, and the ECC decoder uses these check bits to detect and correct errors during retrieval, acting as a mediator between the imperfect physical storage medium and the required data integrity
2Area of stationary object
If pattern size is reduced to increase integration density, then more memory cells fit in limited area, but cell-to-cell interference increases
Solution Approach 1:
The scrambler performs preliminary randomization of data patterns before writing to the memory array. By converting sequential or repetitive bit patterns into randomized patterns in advance, the system prevents the formation of harmful bit patterns that could cause read disturbances or cell-to-cell interference in densely packed memory cells
Solution Approach 2:
The patent changes the parameter of data bit patterns through scrambling operations. The scrambler transforms the original data into a randomized form with different statistical properties, ensuring that no harmful patterns exist in the stored data, thereby mitigating interference effects in high-density memory configurations
3Quantity of substance
If MLC techniques are used to store multi-bits per cell, then storage capacity increases, but data errors occur more frequently
Solution Approach 1:
The system applies preliminary scrambling to the data before it undergoes MLC encoding and storage. This pre-randomization ensures that the multi-bit data stored in each cell does not exhibit harmful patterns that could exacerbate read disturbances or interference, thereby reducing error rates while maintaining high storage capacity
Solution Approach 2:
The ECC encoding circuit acts as an intermediary that adds redundancy to the multi-bit data stored in each cell. The check bits generated by the ECC encoder accompany the data through storage and retrieval, enabling error detection and correction that compensates for the higher error propensity of MLC cells
4Measurement precision
If read margin is narrow due to cell nature, then memory device exhibits high error rate, but changing cell structure is limited
Solution Approach 1:
The ECC decoder serves as an intermediary that compensates for narrow read margins. By using the check bits to detect and correct errors in the read data, the system overcomes the limited read margin inherent to certain memory cell types without requiring structural changes to the cells themselves
Solution Approach 2:
The system implements feedback through the ECC decoding process, where the syndrome calculation and error correction operations use the check bits to identify and fix errors in the read data. This feedback mechanism continuously monitors and corrects errors, maintaining data integrity despite narrow read margins
Data Source
AI summary
A memory system apparatus may be provided. The memory system may have memory controller. The memory controller may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.