Memory Module Scratchpad Decouples Data Operations

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Solution Overview

Problem

Modern computer systems are limited by the inefficiency of bulk memory devices like DRAM, which have longer access times, leading to performance bottlenecks due to the speed and efficiency of operations using the memory bus.

Innovation Solution

A data processing system that includes a memory controller and a memory module with a scratchpad that reduces access overhead by selectively copying data between bulk memory and the scratchpad, using die-to-die bonding technology and a processor-in-memory (PIM) to improve data access speed and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If bulk memory devices like DRAM are used for high density and low cost, then storage capacity is improved, but access time increases and performance is limited

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess time
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The memory system is segmented into two distinct parts: bulk memory for high-density storage and a scratchpad memory for fast access. This segmentation allows each memory type to operate in its optimal performance range, with the scratchpad handling time-critical data and bulk memory providing economical high-capacity storage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scratchpad memory acts as an intermediary between the CPU and bulk memory. It buffers data transfers, allowing the CPU to access frequently needed data quickly while bulk memory maintains high-density storage capacity. This intermediary layer decouples the speed requirements from the storage capacity requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If memory controllers use intelligent re-ordering strategies to improve memory bus efficiency, then bus utilization is improved, but access overhead and complexity increase

Engineering Contradiction:
Improvememory bus efficiencyVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The complex re-ordering and scheduling logic is extracted from the memory controller and implemented instead in the scratchpad memory management unit. This allows the controller to maintain simpler operation while the scratchpad handles intelligent data movement and re-ordering, reducing controller complexity while preserving bus efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Speed

If scratchpad memory is used to reduce access overhead, then access speed is improved, but device complexity and data movement requirements increase

Engineering Contradiction:
Improveaccess speedVSAvoidmemory module complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The scratchpad memory is merged with the bulk memory module into a unified memory package. This integration allows the scratchpad to be physically close to the bulk memory, enabling efficient data movement between them while presenting a unified interface to the CPU, thereby reducing overall system complexity despite the added functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10817422B2Data processing system with decoupled data operations
Publication Date: 2020.10.27 ADVANCED MICRO DEVICES INC
  • US10817422B2 patent drawing
  • US10817422B2 patent drawing
  • US10817422B2 patent drawing

AI summary

In one form, a data processing system includes a host integrated circuit having a memory controller, a memory bus coupled to the memory controller, and a memory module. The memory module includes a bulk memory and a memory module scratchpad coupled to the bulk memory, wherein the memory module scratchpad has a lower access overhead than the bulk memory. The memory controller selectively provides predetermined commands over the memory bus to cause the memory module to copy data between the bulk memory and the memory module scratchpad without conducting data on the memory bus in response to a data movement decision.