Memory Scribe Structure With Polymer Liner for Crack-Free Dicing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low-k insulating materials in semiconductor devices, such as silicon oxycarbide and silicon carbonitride, exhibit weak thermo-mechanical characteristics, leading to adhesion issues and brittleness, which result in cracks during the dicing process, reducing yield and causing discontinuous conductive seed layers for electroplating.
Innovation Solution
The use of polymer liners to cover edge surfaces of low-k films, providing support and smoothing the surface to prevent cracks, and the deposition of a barrier and conductive seed layer in a seamless manner for successful electroplating of conductive pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k insulating material is used to reduce parasitic capacitance, then high speed operation is achieved, but adhesion to conductive layers deteriorates and cracks occur during dicing
Solution Approach 1:
The patent uses a composite structure consisting of low-k insulating material combined with polymer liner material. The polymer liner (e.g., polyimide, phenolic resin) is applied to the edges of the low-k film to provide mechanical support and improve adhesion, while the low-k material core maintains its low dielectric constant for high-speed operation. This composite approach allows the device to achieve both fast signal transmission and structural reliability during dicing.
2Reliability
If groove is formed in scribe region to reduce cracks during dicing, then crack propagation is reduced, but edge surfaces become concave causing discontinuous conductive seed layer
Solution Approach 1:
The patent applies polymer liner material to the edges of the low-k insulating film before the dicing process. This preliminary action creates a protective layer that compensates for the concave shape formed by grooves, ensuring that the edge surfaces remain sufficiently flat and continuous for subsequent conductive seed layer deposition and electroplating operations.
Solution Approach 2:
The polymer liner acts as an intermediary layer between the low-k insulating material and the conductive seed layer. It fills the concave regions created by grooves and provides a continuous, flat surface that enables proper adhesion and continuity of the conductive seed layer, thereby mediating between the structural requirements for crack resistance and the surface flatness requirements for electroplating.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mechanical stability of the semiconductor device, reduces crack propagation, and ensures continuous conductive seed layers for effective electroplating, thereby improving the yield and reliability of semiconductor chips.
Implementation Method 1
a low-k film has lower adhesion to its adjacent conductive layer or conductive components
Implementation Method 2
a conductive seed layer may be formed as an initial step of electroplating of the conductive material
Data Source
AI summary
Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.