Memory Controller Scrub Address Sequencing for Row-Fault Logging
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Solution Overview
Problem
Existing memory systems face inefficiencies in error detection and log collection during scrub operations, particularly in cases where row-fault errors occur intensively, leading to potential loss of critical error log information and reduced system performance.
Innovation Solution
A memory controller that generates scrub addresses with a specific sequence, dividing column and row addresses into bit groups and altering their allocation order, ensuring thorough error checking and distributed log collection across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address sequences are used during scrub operations, then the scrub operation can be performed simply, but critical error log information may be lost when row-fault errors occur intensively
Solution Approach 1:
The column address is divided into two separate bit groups (first column bit group and second column bit group), and the address sequence is reorganized to allocate these groups at different positions (LSB and MSB respectively). This segmentation allows scrub operations to be distributed across different memory regions more effectively, preventing concentration of scrub operations in specific rows and thereby preserving critical error log information.
Solution Approach 2:
The patent changes the traditional address allocation dimension by reordering the sequence of address bits. Instead of the conventional order, the first column bit group is allocated to LSB, followed by row address bits, and the second column bit group is allocated to MSB. This dimensional reorganization distributes scrub operations across different memory regions, improving error detection reliability while preventing information loss.
2Productivity
If scrub operations are concentrated in specific memory regions, then error checking can be performed efficiently, but system performance deteriorates due to intensive row-fault errors
Solution Approach 1:
By segmenting the column address into two bit groups and allocating them to different positions in the address sequence (LSB and MSB), the patent distributes scrub operations across multiple memory regions rather than concentrating them in specific rows. This segmentation maintains scrub operation efficiency while preventing performance deterioration from intensive row-fault errors.
Solution Approach 2:
The reorganized address sequence creates different local access patterns in different memory regions. By allocating the first column bit group to LSB and the second column bit group to MSB, the patent ensures that scrub operations are locally distributed across memory regions, preventing any single region from being overwhelmed and maintaining overall system performance.
Data Source
AI summary
A memory controller includes a scrub control circuit configured to generate a scrub command for instructing a scrub operation; and an address generation circuit configured to generate a scrub address having an address sequence in which a first column bit group of a column address, a row address, and a second column bit group of the column address are sequentially allocated from a least significant bit (LSB) to a most significant bit (MSB), and change a value of the scrub address according to the scrub command.