Memory Error Scrub Mode for On-Die ECC Error Visibility
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Solution Overview
Problem
Traditional memory subsystems fail to detect and correct errors within DRAM devices effectively, leading to undetected error accumulation due to the lack of insight from system-level ECC into on-die ECC operations, which can result in reduced reliability and accessibility of memory systems.
Innovation Solution
Implementing an error check and scrub (ECS) mode in memory devices that enables internal error monitoring and correction, allowing the memory device to count errors and expose error information to the host system, thereby facilitating improved system-level error correction and reliability through error tracking and correction mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is implemented in DRAM devices, then single bit errors can be corrected internally, but error information remains hidden from the host system and errors can accumulate undetected
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors error correction operations internally and reports error information back to the host system through status registers. This allows the host to be informed about errors that occur and are corrected by on-die ECC logic, preventing error accumulation while maintaining the benefits of internal error correction.
Solution Approach 2:
The patent introduces status registers as an intermediary component between the on-die ECC logic and the host system. These registers store error information generated by the ECC logic and make it accessible to the host, thereby bridging the information gap without interfering with the error correction process.
2Measurement precision
If system level ECC is used, then errors can be detected at the host, but the system has no insight into what error correction has been performed at the memory device level
Solution Approach 1:
The patent implements feedback from the memory device's on-die ECC logic to the host system through status registers. This feedback provides the host with information about errors detected and corrected at the memory device level, complementing system-level ECC detection and providing complete visibility into the error management process.
Solution Approach 2:
The patent divides error monitoring into two segments: on-die ECC logic that handles single bit error correction at the memory device level, and system-level ECC that detects errors at the host level. Status registers bridge these segments by reporting on-die correction activities to the host, enabling both levels to work together with full visibility.
3Quantity of substance
If DRAM manufacturing processes scale to smaller geometries, then memory density increases, but DRAM errors are projected to increase
Solution Approach 1:
The patent implements self-service error correction at the memory device level through on-die ECC logic that automatically detects and corrects single bit errors without host intervention. This self-service capability maintains reliability as manufacturing processes scale, allowing higher density to be achieved without proportional increases in error rates affecting system performance.
Solution Approach 2:
The patent applies preliminary error correction at the memory device level before data is transferred to the host system. By correcting errors early in the data path through on-die ECC, the system prevents errors from propagating, allowing aggressive scaling while maintaining data integrity.
Data Source
AI summary
An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.