Radiation-Hardened Memory Scrub Engine With Redundant EDAC

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

CMOS integrated circuits operating in extreme environments are prone to increased single event errors due to radiation exposure, leading to reliability issues and failure, as they are sensitive to ionizing radiation which causes parasitic effects and latch-up, making it difficult to maintain error-free operation.

Innovation Solution

The integration of buried guard ring (BGR) and parasitic isolation device (PID) structures, combined with spatially redundant circuitry such as dual interlocked storage cell (DICE) circuits and error detection and correction (EDAC) mechanisms, provides enhanced radiation hardening by reducing parasitic charge sharing and increasing channel isolation, thereby minimizing the impact of radiation-induced errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If CMOS circuits are scaled down to smaller critical dimensions and operation voltage is reduced, then device density and power efficiency are improved, but sensitivity to radiation single event effects increases

Engineering Contradiction:

Improvepower efficiencyVSAvoidsensitivity to radiation single event effects

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent divides the circuit into spatially redundant segments (multiple storage cells) where each segment can independently store the same data. This segmentation allows the circuit to tolerate radiation-induced errors in individual segments while maintaining overall functionality, thereby enabling continued operation at reduced voltage and scaled dimensions without proportionally increased radiation sensitivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements error detection and correction mechanisms that are prepared in advance to cushion against radiation effects. The spatially redundant storage cells are configured beforehand to detect and correct single event effects, providing a protective buffer that allows the circuit to operate reliably at smaller dimensions and lower voltages where radiation sensitivity would otherwise be problematic.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If spatially redundant circuitry is implemented to reduce radiation sensitivity, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveerror-free operationVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple storage cells into a unified spatially redundant structure where the same data is stored across multiple cells. This combining approach achieves error detection and correction capabilities while maintaining a relatively compact implementation, balancing the trade-off between reliability improvement and device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The spatially redundant storage cells serve multiple functions: they store data, detect errors, and correct errors. This multi-functionality reduces the need for separate dedicated error correction circuits, thereby limiting the increase in device complexity while achieving improved reliability through spatial redundancy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Object-affected harmful factors

If buried guard ring and parasitic isolation device structures are added, then radiation hardening is enhanced, but manufacturing complexity increases

Engineering Contradiction:

Improveparasitic charge sharingVSAvoidfabrication process

Core Design Contradiction:

Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent embeds buried guard ring and parasitic isolation device structures within the existing CMOS fabrication process flow. These radiation hardening features are nested into the standard manufacturing sequence, allowing them to be integrated without requiring entirely new fabrication equipment or processes, thereby limiting the increase in manufacturing complexity while achieving reduced parasitic charge sharing.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS9201726B2Memory circuit incorporating radiation-hardened memory scrub engine

Publication Date: 2015.12.01 SILICON SPACE TECH D B A VORAGO TECH

AI summary

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.