Memory Error Check Scrub Prioritization During Read Operations
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Solution Overview
Problem
In semiconductor devices, the increased speed of data transmission leads to a higher probability of errors, necessitating improved methods to ensure data reliability, particularly during read operations.
Innovation Solution
A semiconductor system that latches a command address when an error occurs, performs an error check scrub (ECS) operation on the corresponding memory cell, and then sequentially corrects errors in multiple memory cells, prioritizing the ECS operation based on latch row and column addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ECS operation is performed sequentially on all memory cells, then all internal data errors can be corrected, but the time required to correct errors increases
Solution Approach 1:
The patent implements a priority mechanism that identifies and corrects errors in currently accessed memory cells (those with valid latch row and column addresses) before proceeding to other memory cells. This preliminary action on high-priority cells reduces the overall error correction time while maintaining data reliability, as the most critical errors are addressed first rather than waiting for a complete sequential scan.
Solution Approach 2:
The patent applies different correction priorities to different memory cells based on their current state and accessibility. Memory cells that are currently accessed (have valid addresses) receive priority correction, while other cells are corrected in the background. This local quality approach optimizes the correction process by focusing resources on the most relevant errors rather than treating all memory cells uniformly.
2Loss of time
If the command address is latched when an error occurs, then the affected memory cell can be identified and corrected preferentially, but the system complexity increases
Solution Approach 1:
The patent utilizes the existing command address that is already being processed by the memory system to identify the affected memory cell. Instead of requiring a separate error detection and address capture mechanism, the system leverages the naturally occurring command address during normal operations. This self-service approach minimizes additional circuitry while enabling preferential correction of the erroneous cell.
Solution Approach 2:
The latch circuit serves multiple functions: it captures the command address for timing purposes during normal operations and simultaneously provides the address information needed for error correction when errors are detected. This multi-functionality reduces the need for dedicated error handling circuitry, thereby limiting the increase in system complexity while still enabling preferential error correction.
Data Source
AI summary
A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.