Memory Search Logic for NAND Flash Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory search operations are slow due to high latency and input/output (I/O) speed limitations, which hinder real-time pattern recognition applications that require large memory capacities and quick data matching.
Innovation Solution
Implementing internal search logic within the memory device to minimize I/O interactions and enable parallel searching of multiple memory arrays, reducing the need for extensive external processor intervention and optimizing data access through row and column decode circuitry, cache registers, and control logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is used to provide large storage capacity, then storage capacity is improved, but search speed deteriorates due to latency and I/O speed limitations
Solution Approach 1:
The patent combines the memory array with integrated search logic within the same device, merging storage and processing functions. This allows the memory device to perform search operations internally without requiring external processors, thereby improving search speed while maintaining large storage capacity.
Solution Approach 2:
The patent introduces an intermediary search logic component that sits between the memory array and external processors. This intermediary performs preliminary search operations within the memory device, reducing the need for slow external I/O interactions and accelerating search operations.
2Ease of operation
If external processor intervention is used for searching, then search functionality is achieved, but I/O interactions increase causing slower performance
Solution Approach 1:
The memory device performs search operations on its own without requiring external processor intervention. The integrated search logic enables the memory device to autonomously search its contents, eliminating the need for slow external I/O interactions and reducing the time lost to data transfer.
Solution Approach 2:
The patent segments the search function from the external processor and places it within the memory device. This segmentation allows search operations to be performed independently within the memory device, reducing dependency on external processors and minimizing I/O interaction time.
3Device complexity
If sequential searching is used, then simple processing is maintained, but productivity decreases due to inability to process multiple arrays in parallel
Solution Approach 1:
The patent implements dynamic parallel processing capabilities within the memory device, allowing multiple memory arrays to be searched simultaneously. The search logic can adaptively activate multiple search operations in parallel when multiple arrays need to be searched, significantly improving productivity while maintaining manageable complexity through standardized processing units.
Data Source
AI summary
A memory includes a memory array comprising a plurality of pages and a page buffer. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results.