Memory Device Section Redundancy for Defect Repair
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Solution Overview
Problem
Existing techniques for repairing defective memory cells in semiconductor memory devices are impractical due to the excessive amount of circuitry required to support repairs, especially when defects affect multiple rows or columns, leading to the scrapping of memory devices.
Innovation Solution
The implementation of a memory device architecture that allows for the use of redundant sections to replace defective sections, with a minimal amount of circuitry needed, by recording and comparing high-order address bits to redirect access to redundant rows or columns, and utilizing an addressing circuit to manage the substitution of defective sections with redundant ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant rows or columns are provided to repair defective memory cells, then memory device reliability is improved, but device complexity increases due to the large amount of circuitry needed to support repairs
Solution Approach 1:
The patent segments the memory device into multiple sections, each with its own redundant row and column. Instead of providing redundant rows/columns for the entire memory device, each section independently manages its own defects. This segmentation reduces the overall circuitry complexity while maintaining reliability, as each section only needs minimal repair resources rather than the entire device needing extensive redundancy.
2Adaptability or versatility
If the number of redundant rows and columns is vastly increased to repair more defective cells, then repair capability is improved, but manufacturing cost and device complexity increase immensely
Solution Approach 1:
The patent pre-allocates one redundant row and one redundant column per section during manufacturing, establishing repair capability in advance. This preliminary action ensures that each section has sufficient redundancy to handle typical defects without requiring excessive circuitry. The system is designed upfront with adequate but not excessive redundancy, balancing repair capability with manufacturing cost.
3Reliability
If section-level redundancy is implemented to repair entire sections, then repair effectiveness is improved, but the amount of circuitry required increases
Solution Approach 1:
The patent implements local quality by providing redundancy at the section level rather than uniformly across the entire device. Each section has its own redundant row and column specifically tailored to handle defects within that local region. This localized approach improves repair effectiveness for section-level failures while avoiding the excessive circuitry that would be required for device-wide redundancy schemes.
Data Source
AI summary
Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.