Memory Device Sector Erase Driving Circuit
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Solution Overview
Problem
Conventional memory devices face challenges in performing sector erase operations efficiently, as the number of global word lines required increases with smaller sector unit sizes, leading to increased circuit area and complexity.
Innovation Solution
The memory device employs a driving circuit with a global word line driver and local word line drivers to apply erasing and biasing voltages independently to local word lines, allowing for sector erase functions without being limited by sector unit size, by using a combination of transistors and control signals to manage voltage levels for erased and non-erased states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the sector unit size becomes smaller, then the memory device can store more data with finer granularity, but the number of needed global word lines increases
Solution Approach 1:
The patent divides the memory device into multiple banks, where each bank has its own independent global word line. This segmentation allows different banks to operate independently, enabling smaller sector units without requiring a proportional increase in the total number of global word lines, as multiple banks can share the same global word line resource through time-multiplexed operations.
Solution Approach 2:
The patent introduces a bank dimension to the memory architecture, organizing memory cells in a three-dimensional structure (bank × word line × bit line). This additional dimension allows the system to address smaller sectors by selecting specific banks and word line combinations, rather than requiring more global word lines, effectively solving the problem through spatial reorganization.
2Adaptability or versatility
If the number of global word lines increases, then smaller sector units can be addressed, but the total circuit area increases
Solution Approach 1:
Each global word line is designed to serve multiple banks universally. The same global word line can be applied to different banks at different times, allowing a reduced number of global word lines to support smaller sector units across the entire memory device, thereby reducing the circuit area while maintaining sector erase capability.
Solution Approach 2:
The patent merges the control of multiple banks under a shared global word line infrastructure. By combining bank selection logic with global word line control, the system achieves efficient address mapping that allows smaller sectors to be erased using the same global word line resources, reducing overall circuit area.
3Productivity
If a global word line voltage is applied to erase a memory sector, then all local word lines of the sector are set to erased status, but additional local word line drivers are needed to maintain non-erased states
Solution Approach 1:
The patent applies different voltage levels to different local word lines within the same bank based on their specific operational requirements. During erase operations, only the local word lines corresponding to the target sector receive the erase voltage, while other local word lines maintain their normal voltage levels through dedicated drivers, enabling selective erasure without affecting the entire bank.
Solution Approach 2:
The local word line drivers are designed to dynamically switch between different voltage states (erase voltage, read voltage, idle voltage) based on the current operation being performed. This dynamic control allows the same driver circuit to support multiple operational modes, reducing the need for additional dedicated drivers for each function.
Data Source
AI summary
A memory device comprises a plurality of sectors and a driving circuit comprising a global word line driver and a first local word line driver. The global word line driver applies an erasing voltage to a selected sector of the sectors via a global word line. The first local word line driver, coupled to the global word line, drives a first local word line of the selected sector with a biasing voltage, so that the first local word line has a first voltage level corresponding to a non-erased state.