Memory Data Security Circuitry for Randomized DQ Mapping
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Solution Overview
Problem
Volatile memory devices face data security risks as data can be accessed without authorization by cooling and swapping them between systems, leading to potential data loss and unauthorized access.
Innovation Solution
Incorporating data security circuitry that randomizes DQ terminal assignments and burst orders upon initialization, using randomizers and scramblers to generate new data transfer and burst swap patterns with each power cycle, ensuring data remains scrambled and uninterpretable across power cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored in volatile memory, then data can be accessed and retrieved, but data can be accessed without authorization by cooling and swapping between systems
Solution Approach 1:
The patent implements dynamic terminal assignments where data terminals are randomly mapped to memory cell columns upon initialization. This dynamic reconfiguration ensures that the same physical terminal accesses different logical memory locations across power cycles, preventing unauthorized data retrieval while maintaining normal operational access through the same randomization process.
Solution Approach 2:
The patent changes the mapping parameter between data terminals and memory cell columns by generating random assignment patterns. This parameter change occurs at initialization and ensures that terminal-to-column mappings are different across power cycles, making it impossible to retrieve stored data without authorization while maintaining full functionality during normal operation.
2Object-affected harmful factors
If randomization of terminal assignments is implemented, then data security is improved across power cycles, but device complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the memory device autonomously generates random terminal assignments and manages the scrambling/descrambling process internally. A small dedicated circuit within the memory device handles the randomization and mapping management without requiring external controller intervention, thereby achieving enhanced security while minimizing the increase in device complexity.
Solution Approach 2:
The patent performs preliminary randomization of terminal assignments during initialization before normal operation begins. By pre-configuring the random mappings and storing the assignment patterns in dedicated circuitry, the system establishes security measures in advance, avoiding the need for complex real-time randomization during data operations and reducing overall device complexity.
Data Source
AI summary
Memory devices with data security circuitry (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of DQ terminals, and circuitry configured to, upon each initialization of the apparatus, (i) set a data transfer pattern for the apparatus to a random one of a plurality of data transfer patterns for the apparatus, and/or (ii) set a burst swap order for the apparatus to a random one of a plurality of burst swap orders for the apparatus. Each data transfer pattern can define a different allocation of memory cells of the memory array to DQ terminals of the plurality of DQ terminals. Additionally, or alternatively, each burst swap order can define a different order in which the apparatus is configured to parallelize or serialize data received or output, respectively, via the plurality of DQ terminals.