Memory Security Block with Dual CPUs for Non-Suspended Tasks
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Solution Overview
Problem
Existing security processes in built-in devices are susceptible to suspension due to interrupt processes, leading to potential information leaks and increased latency, and are not efficiently managed by operating systems.
Innovation Solution
A memory system with a security block (SECB) incorporating two dedicated CPUs - a kernel CPU and a task CPU - that manage security processes without suspension, using a communication mechanism via a mail box and shared memory to prioritize and schedule tasks, and optimize power consumption through controlled mutex usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated CPU is used to perform security function independently, then security process can be isolated from OS scheduling, but the security process is still susceptible to suspension by interrupt processes and CPU exceptions
Solution Approach 1:
The security block is divided into two independent CPU units: a kernel CPU that handles interrupt processes and system management, and a task CPU that executes security tasks. This segmentation allows the security task execution to be isolated from interrupt suspensions, as the kernel CPU absorbs interrupt handling while the task CPU maintains continuous security process execution.
2Ease of operation
If OS scheduler controls security task execution, then task prioritization is possible, but security process cannot restart unless OS queue conditions are fulfilled causing latency
Solution Approach 1:
A mail box mechanism serves as an intermediary communication channel between the host CPU and the security block's task CPU. This mail box allows the task CPU to receive task assignment instructions and status notification requests independently of OS scheduling, enabling the security process to restart and execute immediately when conditions are met, without waiting for OS queue processing.
3Adaptability or versatility
If interrupt process is mounted to realize device functions, then device operability is achieved, but security process must be suspended causing information leak risks
Solution Approach 1:
The CPU functionality is segmented into two independent units: the kernel CPU that handles all interrupt processes and system operations, and the task CPU that exclusively executes security tasks. This segmentation ensures that interrupt processes cannot suspend the security task execution, as they operate on different CPU units. The mail box mechanism provides controlled communication between the two units without exposing security information to interrupt handling contexts.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller includes a security block which provides a security function related to the nonvolatile memory. The security block includes a first CPU and a second CPU. The first CPU performs communication with an external module which requests the security function, accepts an interruption generated in the security block, and performs task management in the security block such that a security process corresponding to the request is performed without suspension considering the security process as one task. The second CPU performs the security process under control of the first CPU.