Microcontroller Memory Security Marker Detection
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Solution Overview
Problem
Current methods for detecting attempts to linearly extract the contents of a microcontroller or processor memory are inefficient and vulnerable to invasive attacks, particularly in preventing the extraction of program code and secret keys.
Innovation Solution
A method involving the insertion of 'security markers' among program instructions, which are detected by a microprocessor core to trigger an alert action if not recognized, using a predefined monitoring rule, and a protection circuit that decrements a counter upon instruction loading to detect linear extraction attempts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If security markers are inserted among program instructions to detect linear extraction attempts, then detection capability is improved, but device complexity increases
Solution Approach 1:
The program code is segmented by inserting security markers among the program instructions. These markers divide the code into segments that can be independently monitored. The microprocessor core detects these markers during execution, enabling detection of linear extraction attempts without requiring complex external monitoring systems.
Solution Approach 2:
The system uses self-service by having the microprocessor core itself perform the detection function during normal execution. The core naturally encounters security markers while executing program instructions, and this inherent execution flow is leveraged to detect extraction attempts. No separate detection hardware is needed - the processing unit serves dual purposes.
2Reliability
If a counter is decremented for each instruction loaded into the instruction register to monitor extraction attempts, then detection reliability is improved, but device complexity increases
Solution Approach 1:
The monitoring function is merged with the existing instruction execution pipeline. The counter decrement operation is combined with the natural instruction loading process - every time an instruction is loaded into the instruction register, the counter is automatically decremented. This merging eliminates the need for separate monitoring hardware while maintaining reliable detection.
Solution Approach 2:
The instruction register and associated control logic are given multi-functionality. Besides their normal role in instruction execution, they now also serve as part of the security monitoring system by triggering counter decrements. This universal use of existing components improves reliability without adding dedicated monitoring device complexity.
3Measurement precision
If security markers are inserted with variable periodicity among program instructions, then detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
Security markers are inserted during the code compilation or memory programming phase, before the microprocessor executes the code. This preliminary action allows the markers to be placed with variable periodicity according to security requirements without affecting runtime performance. The variable spacing provides better detection precision while the pre-processing nature keeps manufacturing manageable.
Data Source
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AI summary
Method for detecting an attempt to linearly extract program code stored in a memory (10) of an electronic circuit (1), the code comprising program instructions which, in order to be read by a microprocessor core (14), are sequentially loaded via an instruction bus (11) into an instruction register (12) for instruction storage controlled at least by a clock signal (clk) and a reset signal, the loading of each instruction into the instruction register (12) taking place on an edge of the clock signal (clk), the code comprising instructions called "security markers" inserted among the program instructions so as to be read during the execution of the program, the method comprising triggering a predefined alert action (300), in the event of non-detection of a security marker, according to a predefined monitoring rule.