Semiconductor Memory Security Circuit Test Pattern Sharing
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Solution Overview
Problem
The high test cost associated with semiconductor memories equipped with security features is due to the need for separate test patterns and complex pattern generation for memory-core-only and total function tests, which increases the burden of testing and costs.
Innovation Solution
A semiconductor memory with an address conversion circuit and a security processing circuit that allows bypassing of security protection, enabling a shared test pattern for different contents, reducing the need for frequent pattern replacements and simplifying the testing process using a memory-specific tester.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test patterns are used for memory-core-only-test and total function test, then test reliability is improved, but test cost and complexity increase
Solution Approach 1:
The patent merges the test pattern generation for memory-core-only-test and total function test into a unified system. The address conversion circuit and security processing circuit work together to generate a single test pattern that can be used for both test types, eliminating the need for separate pattern generation and reduction processes.
Solution Approach 2:
The test pattern generation system is designed to serve multiple functions. The same address conversion circuit and security processing circuit that operate during normal memory function are used during both memory-core-only-test and total function test, allowing a universal test approach that reduces complexity while maintaining reliability.
2Measurement precision
If separate test patterns are used for memory-core-only-test and total function test, then test accuracy is improved, but the burden of generating and replacing test patterns increases
Solution Approach 1:
The address conversion circuit and security processing circuit operate autonomously using the same logic as normal memory operation. During testing, these circuits automatically convert test addresses and apply security processing without requiring external pattern generation, allowing the system to self-test and reducing the time burden of pattern preparation.
Solution Approach 2:
The address conversion circuit is pre-configured with conversion rules and the security processing circuit is pre-programmed with security logic. This preliminary setup allows the circuits to immediately process test patterns without requiring time-consuming pattern generation or replacement during actual testing.
3Reliability
If a memory-specific tester performs total function test with security features activated, then test completeness is improved, but test cost increases considerably
Solution Approach 1:
The patent enables a universal test approach where the same address conversion circuit and security processing circuit used in normal operation are utilized during testing. This eliminates the need for specialized test equipment and allows standard memory testers to perform complete total function tests with security features activated, significantly reducing test costs while maintaining test completeness.
Solution Approach 2:
The memory device's own address conversion and security processing circuits perform the testing functions during total function test. This self-testing capability eliminates the need for expensive external specialized test equipment, allowing standard testers to achieve complete security feature verification at lower cost.
Data Source
AI summary
A memory-specific tester has a buffer storing input pattern data and output expectation data. An address included in the input pattern data read from the buffer is sent to a semiconductor memory, and is then subjected to descrambling at a security circuit. The descrambled address is converted at an address conversion circuit to an address designating a region for storing a check pattern in a memory core. Data given from the memory core (check pattern) is subjected to scrambling at the security circuit, and is then sent to the memory-specific tester. The memory-specific tester makes comparison between expectation data and the data read from the semiconductor memory.