Memory Device Segment Repair Circuit
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Solution Overview
Problem
The increasing number of defective cells in memory devices due to subdivided manufacturing processes hampers the production yield and makes it difficult to achieve compact and mass storage memory devices, as it requires additional spare cells for repair, which complicates the realization of efficient memory capacity.
Innovation Solution
A memory device with a repair circuit that minimizes spare cells and fuse circuits by using segment match determining and column match determining circuits to replace defective cells with spare cells in segment units, efficiently repairing cells and enhancing data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional spare cells are used to repair defective cells, then data reliability is improved, but device complexity and area increase
Solution Approach 1:
The memory device is divided into multiple segments, with each segment having its own repair circuit that can independently repair defective cells. This segmentation allows the repair function to be distributed across multiple smaller units, improving reliability without requiring a single large complex repair system, thereby resolving the contradiction between reliability and device complexity
Solution Approach 2:
Spare cells are pre-configured and organized in advance within each segment, ready to immediately replace defective cells when failures occur. This preliminary preparation of repair resources ensures high data reliability while keeping the repair mechanism simple and straightforward, avoiding the need for complex dynamic repair logic
2Reliability
If additional spare cells are used to repair defective cells, then data reliability is improved, but memory capacity is reduced
Solution Approach 1:
By dividing the memory device into segments with localized spare cells, the spare cells are efficiently utilized within each segment rather than requiring excessive global spare capacity. This segmentation approach maximizes the use of available memory capacity while ensuring sufficient repair capability for each segment, resolving the contradiction between reliability and memory capacity
Solution Approach 2:
Each segment is equipped with its own dedicated spare cells and repair circuitry, creating local repair capability. This local quality approach ensures that repair resources are optimally distributed and utilized, providing high reliability for each segment without requiring excessive total spare capacity across the entire device, thereby preserving maximum memory capacity
3Ease of repair
If more fuse circuits are used for cell repair, then repair capability is improved, but manufacturing complexity increases
Solution Approach 1:
The fuse circuits are segmented and distributed across different repair circuits, with each segment managing its own fuse resources. This segmentation simplifies the manufacturing process by breaking down the complex fuse circuit implementation into smaller, more manageable units, while still providing comprehensive repair capability across the entire memory device
Data Source
AI summary
A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.


