Nonvolatile Memory Device Segmentation for Error Detection
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Solution Overview
Problem
Conventional memory devices connected to host circuits face inefficiencies in reading and writing data and error detection, leading to communication reliability issues due to faulty contacts and inadequate error detection mechanisms.
Innovation Solution
A memory device with a nonvolatile memory cell array and a memory control circuit that separates data and error detection codes into distinct areas, allowing for efficient reading and writing by incorporating error detection within data access units and using mirror data for consistency checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection codes are appended at the end of actual data, then error detection capability is provided, but reading and writing efficiency deteriorates due to the need to separate and process both data and error codes
Solution Approach 1:
The memory cell array is divided into a rewriteable area and a read-only area. In the rewriteable area, N-bit access units contain both actual data and error detection codes interleaved together, enabling error detection during normal read/write operations. In the read-only area, N-bit access units contain only actual data, eliminating the need for separation operations and improving efficiency for data retrieval.
2Duration of action of stationary object
If communication continues with unresolved communication faults, then operation persistence is maintained, but data error risks increase
Solution Approach 1:
Error detection codes are incorporated into the memory cell array structure beforehand, allowing continuous operation without fault resolution while maintaining data integrity. The error detection capability is built-in advance, enabling the system to detect and manage communication faults without stopping operation, thus maintaining both persistence and reliability.
3Productivity
If N bits constituting one access unit contain both actual data and error detection code, then error detection efficiency is improved, but device complexity increases
Solution Approach 1:
The memory cell array is segmented into two distinct areas with different configurations: the rewriteable area contains N-bit access units with both actual data and error detection codes for efficient error detection during write operations, while the read-only area contains only actual data for efficient reading. This segmentation allows each area to be optimized for its specific function, managing complexity through functional separation.
Data Source
AI summary
A memory includes a nonvolatile memory cell array, and a memory control circuit which carries out writing of data to and reading of data from the memory cell array in access units of N bits where N is an integer equal to 2 or greater. The memory cell array includes a rewritable area in which both writing of data and reading of data are permissible, and a read-only area in which writing of data is prohibited and reading of data is permissible. The rewritable area is configured so that the N bits constituting one access unit contain both actual data and an error detection code. The read-only area is divided between an actual data area in which the N bits constituting one access unit contain actual data, and an error detection code area in which the N bits constituting one access unit contain error detection codes.