Memory Architecture Segmentation for Leakage Reduction
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Solution Overview
Problem
Current semiconductor memory architectures face significant challenges in minimizing current leakage during standby and deep power-down modes, leading to high power consumption, especially in small geometry circuits, which affects the performance and efficiency of mobile devices.
Innovation Solution
A memory architecture with hierarchical power management, where power supplies are disconnected from unaccessed memory blocks and only connected to the block in use, combined with a databus precharge scheme that switches between idle and active voltages to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If power supplies are connected to all memory blocks, then memory access speed is improved, but power consumption increases due to current leakage
Solution Approach 1:
The memory array is divided into multiple independently powerable blocks (first block, second block, third block, fourth block). Each block has its own local power grid that can be selectively connected to power supplies. This segmentation allows only the accessed block to receive power during standby mode, reducing leakage current from unaccessed blocks while maintaining fast access speed when a block is activated.
Solution Approach 2:
The power connection state of each memory block is dynamically changed based on access requirements. Power supply connections are switched on demand to connect to the accessed block and switched off for unaccessed blocks. This dynamic power management enables the system to adapt between high-speed access mode (power connected) and low-power standby mode (power disconnected), resolving the contradiction between speed and power consumption.
2Use of energy by moving object
If power supplies are disconnected from unaccessed memory blocks, then power consumption is reduced, but memory access time increases due to power connection switching
Solution Approach 1:
The power supply connection to the accessed memory block is established in advance before the actual memory access operation begins. The control circuitry predicts or determines which block will be accessed and pre-connects its power supply, ensuring that when the access operation starts, the block is already powered and ready for immediate operation, eliminating power connection delay.
Solution Approach 2:
The system employs periodic power connection switching synchronized with memory access patterns. Power supplies are connected and disconnected in periodic cycles corresponding to access sequences, allowing the system to maintain optimal power states while minimizing access delays through rhythmic, predictable power management.
3Reliability
If all memory blocks remain powered during standby mode, then data retention is ensured, but current leakage increases significantly
Solution Approach 1:
The power supply connection is extracted from unaccessed memory blocks during standby mode, completely removing the source of leakage current from those blocks. Only the accessed block maintains its power connection and data retention capability. This extraction approach eliminates unnecessary energy loss while preserving data integrity in the active block.
Solution Approach 2:
Different power states are applied to different memory blocks based on their access status. The accessed block receives full power for data retention, while unaccessed blocks are powered down. This local differentiation of power quality allows the system to optimize data retention only where needed, minimizing overall current leakage across the entire memory array.
Data Source
AI summary
A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.