Memory Device Segmentation for Parasitic Isolation

The memory device is divided into multiple independently controllable blocks, each with its own selection gate transistors. By segmenting the memory into blocks and applying voltage selectively to specific blocks, the patent prevents parasitic transistor activation in non-selected blocks while enabling reliable reading in the selected block. The selection gate transistors act as isolation switches that segment the current paths between different memory strings.

Different voltage levels are applied to different regions of the memory device based on their selection state. The selected block receives a first voltage level that enables reading, while non-selected blocks receive a second voltage level that keeps parasitic transistors inactive. This local differentiation of voltage conditions ensures that only the intended memory string conducts current during reading, eliminating interference from parasitic transistors in other regions.

The three-dimensional memory structure is segmented into multiple blocks along the vertical direction, with each block having independent selection gate control. This segmentation allows the complex 3D structure to be managed as multiple simpler 2D-like layers, reducing voltage control complexity. Each block can be independently activated, simplifying the overall control scheme despite the 3D architecture.

The patent introduces a vertical dimension to the memory structure by stacking multiple memory blocks along the z-axis. This dimensional expansion increases storage capacity without proportionally increasing voltage control complexity, because the selection gate transistors provide hierarchical control - first selecting a block vertically, then selecting a string within the block. The shared pillar structure further simplifies control by allowing multiple strings to share common elements.

The selection gate transistors are activated in advance before the actual reading operation begins. By pre-establishing the correct voltage state on the selection gates, the patent ensures that only the intended memory string is conductive before data retrieval starts. This preliminary isolation prevents parasitic current paths from forming during the reading process, improving accuracy without requiring additional corrective steps.

The patent combines multiple functions into the selection gate transistor structure: it serves as both the isolation switch for preventing parasitic transistor activation and the enable switch for initiating reading. By merging these functions into a single control mechanism, the patent reduces the number of separate voltage application steps needed, thereby reducing time loss while maintaining reading accuracy.