Semiconductor Memory Device Segmented Block Architecture
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Solution Overview
Problem
NAND flash memory devices face challenges in suppressing the influence of capacitance coupling between adjacent cells, leading to fluctuations in threshold voltage, which degrades writing performance, especially when storing multiple bits per cell.
Innovation Solution
A semiconductor memory device and system that employs a combination of first and second memory cells, where the first cell stores k bits and the second cell generates h bits from i bits stored in the first cell, allowing for efficient data storage and reduced write time by using a 2-level block for initial data writing and a multilevel block for fine tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written in multilevel blocks to increase storage capacity, then storage efficiency is improved, but writing speed deteriorates due to capacitance coupling between adjacent cells
Solution Approach 1:
The memory block is divided into two distinct types: 2-level blocks for initial data writing and multilevel blocks for fine-tuning. This segmentation allows the writing process to be split into two phases, where the majority of data is quickly written to 2-level blocks without capacitance coupling issues, and only necessary corrections are made in multilevel blocks, thus resolving the contradiction between storage capacity and writing speed.
Solution Approach 2:
Data is preliminarily written to 2-level blocks before being transferred to multilevel blocks. This preliminary action enables the system to take advantage of the faster writing speed of 2-level blocks for the bulk data operation, while reserving multilevel blocks for precise threshold voltage adjustment only when needed, thereby improving overall writing performance.
2Productivity
If data is written in 2-level blocks to improve writing speed, then writing performance is improved, but storage capacity efficiency deteriorates
Solution Approach 1:
The system merges the advantages of both 2-level and multilevel blocks by combining them in a unified memory architecture. 2-level blocks provide fast writing speed while multilevel blocks provide high storage capacity. By strategically using both types of blocks together, the system achieves both high writing speed and efficient storage capacity utilization.
Solution Approach 2:
Data is preliminarily written to 2-level blocks which offer faster writing speed, and then selectively transferred to multilevel blocks for fine-tuning. This preliminary action in 2-level blocks allows the system to benefit from their speed advantage during the bulk writing phase, while the multilevel blocks handle the capacity-intensive fine-tuning operations.
3Productivity
If adjacent cells are written simultaneously to increase throughput, then writing throughput is improved, but threshold voltage stability deteriorates due to capacitance coupling
Solution Approach 1:
The writing operation is segmented into two phases using two different block types. 2-level blocks handle the initial bulk writing with high throughput, while multilevel blocks handle the fine-tuning phase. This segmentation allows simultaneous writing in 2-level blocks without capacitance coupling issues, while multilevel blocks perform precise adjustments sequentially, thus maintaining both high throughput and threshold voltage stability.
Solution Approach 2:
2-level blocks act as an intermediary structure between the data source and multilevel blocks. Data is first written to 2-level blocks which are immune to capacitance coupling problems, and then selectively transferred to multilevel blocks for fine-tuning. This intermediary approach allows high-throughput writing without compromising threshold voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances writing speed and performance by reducing the impact of capacitance coupling and optimizing data storage capacity, allowing for faster and more reliable writing of multiple bits per cell.
Implementation Method 1
capacitance coupling of cells adjacent to each other tends to increase. Therefore, there is a problem that a threshold level of a cell in which data has been written in the first place fluctuates with writing in an adjacent cell.
Data Source
AI summary
A first memory cell stores data of k bits in one cell. A second memory cell stores data of h bits (h<k) in one cell. Data of i bits (i<=k) is stored in the first memory cell, and data of h bits (h<i) generated from the i-bit data is stored in the second memory cell.