3D Memory Device Segmented Blocks and Pitch Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices with three-dimensional memory cell arrays face challenges in simplifying structure and improving operation characteristics, particularly in efficiently managing data storage and retrieval operations.
Innovation Solution
A memory device design featuring a substrate with alternating semiconductor and insulating layers, word lines, and transistors arranged in a specific pitch configuration, along with a peripheral circuit structure that includes select gate line decoders and bit line selection circuits, to enhance data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell array structure is adopted, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent memory blocks (first memory block, second memory block, etc.), each with its own memory cell array. This segmentation allows the large three-dimensional structure to be managed as smaller, more manageable units, reducing overall device complexity while maintaining high storage capacity through the multiplication of blocks.
Solution Approach 2:
The patent employs a three-dimensional stacked architecture where memory cell arrays are arranged vertically across multiple layers. This dimensional transition from planar to vertical stacking dramatically increases storage capacity within the same footprint while the modular block structure manages the resulting complexity.
2Productivity
If multiple memory blocks are provided with independent decoders, then data retrieval efficiency is improved, but device complexity increases
Solution Approach 1:
The decoder functionality is segmented and distributed across memory blocks. Each memory block has its own select gate line decoder, allowing parallel operation of multiple blocks. This segmentation enables simultaneous data retrieval from different blocks, improving overall efficiency while keeping each individual decoder relatively simple.
Solution Approach 2:
Select gate line decoders are pre-configured within each memory block to rapidly decode and activate specific word lines when needed. This preliminary preparation of decoding circuits enables fast data retrieval by eliminating the need for complex sequential decoding processes during actual data access operations.
Data Source
AI summary
According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch.