Memory Structure with Segmented Contacts for Signal Accuracy
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Solution Overview
Problem
Current memory structures face challenges in improving electrical performance without increasing cell size, particularly due to parasitic capacitance and high resistance values in vertical transistors, which affect signal accuracy in conductive devices like sense amplifiers.
Innovation Solution
The memory structure incorporates a vertical transistor array with a capacitor array and bit lines, utilizing contacts divided into three portions to minimize parasitic capacitance and resistance, with aligned and misaligned second portions and uniform third portions to ensure consistent signal delivery to conductive devices in the peripheral region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical transistors are used to save layout area and increase device integration degree, then area utilization is improved, but parasitic capacitance and resistance increase affecting signal accuracy
Solution Approach 1:
The contact structure is divided into three distinct portions: a first portion connected to the bit line, a second portion extending toward the peripheral region, and a third portion connected to the conductive device. This segmentation allows each portion to be optimized independently, reducing overall parasitic effects while maintaining compact layout.
Solution Approach 2:
Different portions of the contact have different geometric characteristics optimized for their specific functions. The first portion has larger cross-sectional area to reduce resistance from the bit line, the second portion is optimized for routing, and the third portion is designed to minimize parasitic capacitance at the conductive device interface, thereby improving signal accuracy locally at each connection point.
2Reliability
If contact structures are extended to reduce resistance, then electrical connectivity is improved, but parasitic capacitance increases
Solution Approach 1:
The contact structure uses varying cross-sectional areas at different portions. The first portion has a larger cross-sectional area to reduce resistance for current flow from the bit line, while the third portion has optimized dimensions to minimize parasitic capacitance at the conductive device interface, thereby simultaneously improving electrical connectivity and reducing harmful parasitic effects.
Solution Approach 2:
The contact structure extends in multiple dimensions with different cross-sectional areas at different locations. By varying the cross-sectional area along the length of the contact, the design optimizes resistance in the horizontal dimension while controlling parasitic capacitance through vertical dimension adjustments, effectively managing both electrical properties.
3Reliability
If third portions of contacts are misaligned to reduce parasitic capacitance, then signal accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The third portions of contacts in different rows are intentionally positioned asymmetrically relative to the memory region, with odd-row contacts and even-row contacts having different lateral positions. This asymmetric arrangement reduces parasitic capacitance between adjacent contacts while the consistent offset pattern maintains manufacturability through standardized alignment procedures.
Data Source
AI summary
Provided is a memory structure including a substrate having a memory region and a peripheral region, a capacitor array, a transistor array, bit lines, and contacts. The capacitor array is on the substrate in the memory region. The transistor array is on and electrically connected to the capacitor array. The bit lines are extended along a row direction in parallel with each other on the transistor array, and are electrically connected to the transistor array. Each of the contacts is connected to one of the bit lines and a conductive device at the substrate in the peripheral region. Each of the contacts includes a first portion, a second portion, and a third portion. The second portion is between the first portion and the third portion. The third portion is electrically connected to the conductive device. Distances between each of the third portions and the memory region are the same.