Memory Device Program Disturb Mitigation via Segmented Control Lines
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Solution Overview
Problem
Conventional memory devices face data corruption issues due to 'program disturb' during programming, where voltage differences between control lines can inject stray charges into memory cells, corrupting stored data, and existing self-boosting techniques introduce additional electric field-related problems.
Innovation Solution
A programming process involving a sequence of two pulse patterns is executed: an inhibit-pulse pattern, where lower voltages are asserted on drain-side control lines compared to source-side control lines, and a program-pulse pattern, where lower voltages are asserted on source-side control lines compared to drain-side control lines, to reduce data corruption by minimizing electric field strength and enhancing self-boosting effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-boosting techniques are used to mitigate program disturb, then data protection is improved, but electric field strength increases causing stray charge injection
Solution Approach 1:
The control lines are segmented into different groups (first group and second group) with different voltage levels applied during programming. This segmentation allows independent control of voltage distribution to mitigate program disturb while controlling electric field strength.
Solution Approach 2:
Different voltage levels are applied to different groups of control lines based on their specific positions and roles. The first group of control lines receives a first voltage level while the second group receives a second voltage level, creating localized voltage differences that protect specific memory cells from program disturb.
2Reliability
If voltage differences are asserted between control lines to protect unselected memory cells, then program disturb is reduced, but stray charge injection increases
Solution Approach 1:
The patent applies voltage differences between control lines in a controlled sequence during the programming operation. By establishing these voltage differences before and during the programming pulse, the system pre-prevents program disturb while managing electric field effects.
Solution Approach 2:
The patent changes voltage parameters dynamically during programming by asserting different voltage levels on different control line groups. This parameter change allows the system to optimize protection against program disturb while controlling the magnitude of electric fields to minimize stray charge injection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the likelihood of data corruption during programming by pre-charging unselected memory cells and maintaining lower electric fields, thereby protecting unselected memory cells from data corruption while ensuring efficient programming of selected memory cells.
Implementation Method 1
the unselected control lines capacitively couple to the unselected data lines, and this capacitive coupling counteracts the effect of the program voltage on the unselected memory cells connected to the selected control line
Implementation Method 2
Electric fields from the pass voltages drive charges toward the memory cells that are at highest risk of program disturb
Implementation Method 3
A programming process involving a sequence of two pulse patterns is executed: an inhibit-pulse pattern, where lower voltages are asserted on drain-side control lines compared to source-side control lines, and a program-pulse pattern, where lower voltages are asserted on source-side control lines compared to drain-side control lines, to reduce data corruption by minimizing electric field strength
Data Source
AI summary
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has a different median voltage than a drain side of the first pulse pattern.