Memory Device With Segmented Refresh Periods
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) requires frequent refresh operations, leading to increased power consumption and delays in read/write operations, especially as memory density and capacity grow, which becomes a significant issue in neural network applications where high accuracy and low power consumption are crucial.
Innovation Solution
A memory system with a first area refreshed at a shorter period and a second area refreshed at a longer period, where data is split and stored across these areas based on its criticality, with a memory controller managing the write and read operations by generating split commands and processing requests to optimize refresh operations and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to ensure data integrity, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The memory cell array is divided into multiple areas (first area, second area, third area) with different refresh periods. The first area uses a standard refresh period (e.g., 7.8 μs), the second area uses a longer refresh period (e.g., 15.6 μs), and the third area uses an even longer refresh period (e.g., 31.2 μs). This segmentation allows different portions of memory to be refreshed at different rates, reducing overall power consumption while maintaining data integrity for frequently accessed data.
Solution Approach 2:
Different areas of the memory cell array are assigned different refresh characteristics based on their specific needs. The first area (for critical data) maintains frequent refresh for high reliability, while the second and third areas (for less critical data) use extended refresh periods to reduce power consumption. This local differentiation optimizes the balance between reliability and energy efficiency for different data types.
2Reliability
If refresh operations are performed frequently, then data integrity is maintained, but read/write operation speed deteriorates
Solution Approach 1:
The memory is segmented into multiple areas with different refresh schedules. By dividing the cell array into first, second, and third areas with progressively longer refresh periods, the system reduces the frequency of refresh operations in less critical areas, thereby reducing delays in read/write operations while maintaining data integrity in critical areas.
Solution Approach 2:
The refresh period is made dynamic and area-specific rather than uniform across the entire memory array. The memory controller dynamically manages refresh operations for different areas based on their specific requirements, allowing critical data to be refreshed frequently while less critical data undergoes refresh at extended intervals, thus optimizing overall system performance.
3Measurement precision
If memory capacity is increased to meet neural network demands, then neural network accuracy is improved, but power consumption due to refresh operations increases proportionally
Solution Approach 1:
The large-capacity memory required for neural network operations is divided into multiple areas with different refresh periods. This allows the system to support high memory capacity while reducing overall refresh power consumption by applying extended refresh periods to less critical data areas, thereby enabling high-accuracy neural network operations with reduced power consumption.
Solution Approach 2:
Different regions of the high-capacity memory are assigned different refresh characteristics based on data criticality. The first area maintains standard refresh for critical neural network data, while the second and third areas use extended refresh periods for less critical data, optimizing the balance between neural network accuracy and power consumption in large-capacity memory systems.
Data Source
AI summary
A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.