Memory Device Segmented TSV Communication
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Solution Overview
Problem
Current memory devices face challenges in reducing physical size and power consumption while maintaining performance, particularly in high-speed data transfer applications like DDR RAM, due to the large number of Through-Silicon-Vias (TSVs) required for data communication between dies.
Innovation Solution
The memory devices break down communication segments into smaller portions and temporarily store them using latches, reducing the number of TSVs needed by communicating these portions sequentially, rather than transferring full data blocks at once, which allows for a reduced number of TSVs dedicated to data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the number of TSVs is reduced to decrease die size, then device compactness is improved, but data transfer capability deteriorates
Solution Approach 1:
The data transfer process is segmented into multiple phases: write phase, read phase, and recovery phase. Each phase uses a subset of TSVs sequentially rather than requiring all TSVs simultaneously, enabling reduced TSV count while maintaining data transfer capability through time-multiplexed operation
Solution Approach 2:
The system dynamically allocates TSVs across different operational phases. During write operations, certain TSVs are dedicated to write commands while others handle read commands. The allocation changes based on the current operational phase, allowing the same physical TSVs to serve multiple functions at different times
2Use of energy by moving object
If the number of TSVs is reduced to improve power efficiency, then energy consumption is decreased, but data communication capability deteriorates
Solution Approach 1:
Data communication is segmented into separate write and read operations that can be performed using different TSV subsets. This segmentation allows the system to activate only the necessary TSVs for each operation, reducing overall power consumption compared to keeping all TSVs active simultaneously
Solution Approach 2:
The system employs periodic alternation between write operations and read operations, with each phase utilizing a specific subset of TSVs. This periodic activation pattern reduces average power consumption by ensuring that not all TSVs are active at the same time, while still maintaining full data communication capability through sequential operation
3Speed
If TSVs are dedicated for data communication, then data transfer speed is improved, but die size increases
Solution Approach 1:
TSVs are designed with multi-functionality to serve both write and read operations, as well as command and data transmission. By making TSVs universal rather than dedicating separate TSVs for each function, the system achieves high data transfer speeds without proportionally increasing the number of TSVs required
Solution Approach 2:
The system dynamically configures TSV assignments based on operational requirements. During high-speed data transfer phases, the necessary TSVs are activated and configured for optimal performance, while less critical TSVs remain inactive, thereby achieving high speed when needed without the permanent overhead of having all TSVs physically present and active
Data Source
AI summary
A memory device includes active circuitry configured to process a segment set that corresponds to a source data, wherein: the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.