Memory Programming via Segmented Voltage Application
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Solution Overview
Problem
Existing memory technologies face challenges in reducing program disturbance, which leads to a wider threshold voltage distribution range and a smaller read window for memory cells in an erased state.
Innovation Solution
The proposed memory system includes a memory array and a peripheral circuit that applies N program voltages to a word line for a first program operation, programming a memory cell to a first threshold voltage, and then applies M program voltages for a second program operation to program both the highest state and another state memory cells to their respective target threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a direct program scheme is used to program memory cells to target threshold voltages, then programming speed is improved, but program disturbance increases and threshold voltage distribution range widens
Solution Approach 1:
The patent segments the programming process into two distinct stages: a first program operation that programs only the highest state memory cells to a first threshold voltage, and a second program operation that programs both the highest state and another state memory cells to their respective target threshold voltages. This segmentation allows the system to use lower program voltages in the first operation, reducing program disturbance to erased state cells while maintaining programming speed through the efficient two-stage approach.
2Productivity
If a direct program scheme is used to program memory cells to target threshold voltages, then programming efficiency is improved, but threshold voltage distribution range widens
Solution Approach 1:
The patent applies preliminary action by first programming the highest state memory cells to a first threshold voltage before performing the second program operation. This preliminary step ensures that the highest state cells are properly programmed at a lower voltage level, preventing them from causing excessive program disturbance during the second operation when both highest state and another state cells are programmed simultaneously. This maintains programming efficiency while controlling threshold voltage distribution.
3Speed
If higher program voltages are used to program memory cells, then programming speed is improved, but program disturbance increases
Solution Approach 1:
The patent implements dynamics by using different program voltages for different operations: a first program voltage for the first program operation and a second program voltage for the second program operation. The first program voltage is specifically designed to be lower than the second program voltage, allowing the system to optimize each operation's voltage level according to its specific requirements. This dynamic voltage adjustment maintains programming speed while minimizing program disturbance to erased state cells.
Data Source
AI summary
An example of the present disclosure disclose a memory comprising a memory array and a peripheral circuit coupled with the memory array. The memory array comprises a plurality of memory cells. The peripheral circuit is configured to: apply N program voltages to a word line coupled with a to-be-programmed memory cell with a target state being the highest state to perform a first program operation, to program the to-be-programmed memory cell with the target state being the highest state to a first threshold voltage, wherein a difference between a target threshold voltage corresponding to the to-be-programmed memory cell with the target state being the highest state and the first threshold voltage is less than a first preset value, and N is a positive integer; and apply M program voltages to the word line to perform a second program operation.