Memory Device Segmented Word Line Erase Potential Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in maintaining high data retention characteristics due to variations in threshold voltages of memory cell transistors, leading to decreased data retention and erroneous reading, especially after data erasure.
Innovation Solution
The memory system employs a dual-potential approach during erase operations, applying a low erase potential to one group of word lines and a high erase potential to another, which reduces the difference in threshold voltages between adjacent memory cell transistors, thereby enhancing data retention and reducing erroneous readings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single erase potential is applied to all word lines, then the erase operation is simple to implement, but threshold voltage variations increase leading to decreased data retention
Solution Approach 1:
The word lines are divided into two groups: first word lines receive a first erase potential while second word lines receive a second erase potential. This segmentation allows different erase conditions to be applied to different regions, reducing threshold voltage variations and improving data retention characteristics.
Solution Approach 2:
Different erase potentials are applied to different word line groups based on their specific requirements. The first word lines receive one erase potential while the second word lines receive another, optimizing the erase characteristics for each group and reducing overall threshold voltage variations.
2Reliability
If high erase potential is applied to all word lines, then erase completeness is improved, but threshold voltage distribution broadens causing erroneous readings
Solution Approach 1:
By segmenting word lines into two groups with different erase potentials, the patent achieves comprehensive erasure while controlling threshold voltage distribution. The first word lines receive a first erase potential and the second word lines receive a second erase potential, ensuring complete erasure without excessive broadening of threshold voltage distribution.
Solution Approach 2:
The patent changes the erase potential parameter across different word line groups. The first word lines are erased with a first erase potential while the second word lines are erased with a second erase potential, optimizing both erase completeness and threshold voltage precision.
3Reliability
If adjacent memory cell transistors have similar threshold voltages, then reading is simplified, but data retention decreases due to threshold voltage overlap
Solution Approach 1:
The patent segments the erase operation into two distinct groups with different potentials, creating well-separated threshold voltage lobes for adjacent memory cell transistors. This segmentation ensures distinct threshold voltage distributions that improve data retention while maintaining readable separation between states.
Solution Approach 2:
Different erase potentials are applied locally to different word line groups, creating distinct threshold voltage characteristics for adjacent memory cell transistors. The first word lines develop one threshold voltage lobe while the second word lines develop another, preventing overlap and improving data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the difference in threshold voltages, improving data retention characteristics and minimizing erroneous readings by forming distinct threshold voltage lobes that prevent overlap and maintain data integrity.
Implementation Method 1
a first potential is applied to the first word line and a second potential different from the first potential is applied to the second word line
Data Source
AI summary
A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.