Non-volatile memory segregating sequential and random data zones
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Solution Overview
Problem
Non-volatile semiconductor memory devices face inefficiencies in garbage collection operations, leading to increased write amplification, power consumption, and reduced endurance and performance due to the need to frequently relocate valid pages during overwrite operations.
Innovation Solution
Implementing a page-based mapping scheme with segregated zones for sequential and random access write commands, where write data and mapping data are buffered in volatile memory before being written to non-volatile memory, and periodically updating a global LBA/PBA map to minimize garbage collection by ensuring entire blocks are overwritten before erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If page-based mapping is used to enable overwrite operations, then writing flexibility is improved, but garbage collection frequency increases
Solution Approach 1:
The memory space is segmented into multiple zones with different mapping strategies. Sequential zones use sequential mapping to minimize garbage collection, while random zones use page-based mapping for flexibility. This segmentation allows the system to enjoy the benefits of both mapping approaches without suffering from their respective drawbacks in a unified space.
Solution Approach 2:
Different mapping qualities are applied to different regions of the memory system. Sequential zones implement sequential mapping with high efficiency and low garbage collection, while random zones implement page-based mapping with high flexibility. Each zone is optimized for its specific access pattern, achieving local optimality that contributes to global system performance.
2Reliability
If garbage collection is performed frequently to maintain valid pages, then data integrity is improved, but write amplification increases
Solution Approach 1:
The memory system is divided into sequential zones and random zones that are independently managed. Sequential zones experience minimal garbage collection due to their sequential access pattern, reducing overall write amplification while maintaining data integrity through the combined mapping strategies of all zones.
Solution Approach 2:
The patent converts the potential harm of frequent garbage collection into a benefit by using sequential zones where sequential writes naturally overwrite previous data without creating garbage. This transforms what would normally be a waste operation into an efficient data update mechanism that maintains integrity without amplification.
3Productivity
If garbage collection is performed frequently to erase invalid pages, then memory availability is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory into sequential and random zones with different mapping strategies, the system reduces the overall frequency of garbage collection operations. Sequential zones require minimal garbage collection, thereby reducing power consumption while maintaining adequate memory availability through the combined capacity of all zones.
4Ease of manufacture
If garbage collection is performed frequently to relocate valid pages, then block erasure is improved, but performance decreases
Solution Approach 1:
The memory system is divided into sequential zones and random zones that are independently managed. Sequential zones experience minimal garbage collection due to their sequential access pattern, reducing overall write amplification while maintaining data integrity through the combined mapping strategies of all zones.
Solution Approach 2:
The system performs preliminary actions by pre-allocating zones for sequential and random access patterns. This allows the system to proactively manage write operations and minimize garbage collection needs before they become problematic, thereby maintaining high performance while ensuring blocks can be erased when necessary.
Data Source
AI summary
A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones.


