Memory SEL Prevention Circuitry with N-Well Biasing
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Solution Overview
Problem
Volatile memory elements in integrated circuits are prone to data loss and semiconductor reliability issues such as latch-up, which can lead to circuit malfunction or destruction due to single-event latch-up events caused by ionizing radiation.
Innovation Solution
The implementation of single event latch-up prevention circuitry, including a clamping circuit, voltage sensing circuit, and well tap driver circuit, which dynamically biases the n-well tap to an elevated voltage to reverse bias the parasitic silicon-controlled rectifier structure, preventing latch-up by shutting off parasitic bipolar junction transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory elements are used in integrated circuits, then the circuit can be fabricated with standard CMOS technology and data can be rapidly accessed, but the memory elements become prone to single-event latch-up events caused by ionizing radiation which can cause circuit malfunction or destruction
Solution Approach 1:
An n-well tap is introduced as an intermediary element between the parasitic bipolar transistors and the power supply. This tap provides a controlled path to manipulate the biasing of the parasitic transistors, allowing them to be shut off during latch-up events without requiring complete circuit redesign or additional complex protection structures
Solution Approach 2:
The invention dynamically changes the voltage parameter of the n-well tap region. By raising the voltage at the n-well tap above the power supply voltage during a latch-up event, the parasitic bipolar transistors are reverse-biased and shut off, thereby preventing the low-resistance path between power supply rails. This parameter change approach allows the same circuit structure to operate in both normal and protection modes
2Reliability
If clamping circuitry is added to prevent latch-up, then single-event latch-up events are mitigated, but the circuit complexity and power consumption increase
Solution Approach 1:
The clamping circuit operates periodically rather than continuously. The voltage sensing circuit monitors for latch-up conditions and only activates the clamping action when needed. This periodic operation significantly reduces power consumption compared to continuously active protection circuits, while still providing reliable latch-up prevention when events occur
Solution Approach 2:
A voltage sensing circuit provides feedback monitoring of the power supply voltage. When a latch-up event causes voltage droop, the sensing circuit detects this change and triggers the clamping circuitry accordingly. This feedback mechanism ensures the protection circuit only consumes significant power when actually needed, rather than operating continuously
3Reliability
If the n-well tap is dynamically biased to elevated voltage to reverse bias parasitic transistors, then latch-up is prevented, but additional circuitry and control mechanisms are required
Solution Approach 1:
Multiple functions are merged into the n-well tap structure. It serves as both a normal operational element during standard circuit operation and as a protection mechanism during latch-up events. By combining these functions into a single structure rather than adding separate protection circuits, the overall device complexity is minimized while still achieving reliable latch-up prevention
Solution Approach 2:
The n-well tap is designed to serve multiple purposes: it functions as a normal well contact during standard operation and simultaneously serves as a latch-up protection mechanism when voltage is applied to raise it. This multi-functionality reduces the need for dedicated protection circuitry, thereby limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates single event latch-up events, reducing the risk of circuit damage and maintaining operational integrity by selectively reversing biasing the n-well region during transient voltage spikes, thereby enhancing the reliability of volatile memory elements in integrated circuits.
Implementation Method 1
dynamically biases the n-well tap to an elevated voltage to reverse bias the parasitic silicon-controlled rectifier structure, preventing latch-up by shutting off parasitic bipolar junction transistors
Data Source
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AI summary
An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.