Semiconductor Memory Select Gate Line Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing data access and storage due to limitations in select gate line and bit line selection during read and write operations, leading to increased capacitance and reduced processing rates.
Innovation Solution
The semiconductor memory device employs a configuration where select gate lines and bit lines are alternately selected and decoupled to reduce capacitance between interconnects, allowing for efficient data access through 1-SGD or 2-SGD select operations, optimizing the read and write processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If select gate lines and bit lines are simultaneously selected during read/write operations, then data access capability is improved, but capacitance between interconnects increases and processing rate decreases
Solution Approach 1:
The patent divides the selection process into two distinct phases: first selecting string units via select gate lines, then selecting specific memory cells within those strings via bit lines. This segmentation allows the system to manage interconnect capacitance in stages rather than simultaneously activating all selection paths, thereby maintaining data access capability while improving processing rate.
Solution Approach 2:
The patent implements preliminary selection of string units through select gate lines before activating bit lines for final cell selection. This preliminary action prepares the data path in advance, allowing subsequent bit line activation to occur with reduced capacitance burden, thus resolving the contradiction between comprehensive data access and processing speed.
2Productivity
If more select gate lines are selected for wider data access, then data throughput is improved, but pre-charge time increases
Solution Approach 1:
The patent segments the selection hierarchy into select gate line level (string unit selection) and bit line level (cell selection). This allows wider data access to be achieved by selecting multiple select gate lines simultaneously for parallel string unit access, while the bit line pre-charge occurs only after this initial selection, reducing the overall pre-charge time penalty.
Solution Approach 2:
The patent performs preliminary selection of multiple string units via select gate lines before initiating bit line pre-charge. This preliminary action enables the system to prepare multiple data paths in parallel at the string unit level, then activate bit lines only for the selected strings, thereby achieving wide data throughput without proportionally increasing pre-charge time.
3Productivity
If select gate lines are selected for parallel access, then processing efficiency is improved, but voltage node stability deteriorates
Solution Approach 1:
The patent segments the voltage management into two stages: first applying selection voltages to select gate lines for parallel string unit access, then subsequently activating bit lines for cell selection. This segmentation allows voltage nodes to be stabilized in stages, with the select gate line voltage distribution occurring first and establishing a stable foundation before bit line activation, thus maintaining voltage stability while achieving parallel processing efficiency.
Solution Approach 2:
The patent implements preliminary voltage distribution to select gate lines before activating bit lines. This preliminary action establishes stable voltage nodes at the string unit level first, creating a controlled electrical environment that enables subsequent bit line activation without compromising overall voltage node stability, even when multiple select gate lines are activated in parallel.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first string unit including a first memory string including a first selection transistor and a first memory cell coupled to the first selection transistor, a second string unit including a second memory string including a second selection transistor and a second memory cell coupled to the second selection transistor, a first select gate line, a second select gate line, a first bit line, a second bit line, and a first word line. Both of the first select gate line and the second select gate line are selected in a first read operation. The first select gate line is selected and the second select gate line is not selected in a second read operation.